Vertical Semiconductor Device Thermal Management via Electrode Segmentation
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Solution Overview
Problem
Conventional semiconductor devices face challenges in managing heat generation from metal wires, particularly in smaller semiconductor elements, leading to temperature rises, and existing solutions are not applicable to vertical semiconductor elements.
Innovation Solution
The proposed solution involves a semiconductor device configuration with a printed circuit board having a first and second circuit pattern, where the drain electrode is on the upper surface and the gate and source electrodes are on the lower surface, bonded via specific materials and metal members to reduce heat generation and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the area where metal wires are bonded on the semiconductor element is reduced to enable downsizing, then the production cost is reduced and device size is decreased, but the amount of heat generated by each metal wire increases and the temperature of the semiconductor element rises
Solution Approach 1:
The patent transitions from a lateral semiconductor element configuration to a vertical semiconductor element configuration. By arranging the source and drain electrodes in a direction perpendicular to the substrate rather than parallel, the invention changes the spatial dimension of heat dissipation, allowing heat to be conducted vertically through the substrate to heat sinks on the opposite side, thereby resolving the temperature rise issue while maintaining downsized device footprint.
Solution Approach 2:
The invention separates the bonding locations of source/drain electrodes from the gate electrode bonding location by using different metal wires. The source and drain electrodes are bonded to different circuit patterns on the substrate, allowing independent heat dissipation paths. This segmentation enables the metal wires to be optimized for current carrying capacity and heat dissipation without being constrained by the gate electrode positioning.
2Device complexity
If the number of metal wires to be wired to the source electrode is decreased due to smaller bonding areas, then the wiring complexity is reduced, but the amount of heat generated by each metal wire increases
Solution Approach 1:
By adopting a vertical semiconductor element configuration, the invention enables more efficient heat dissipation through the substrate thickness dimension. The source and drain electrodes can be positioned at different depths or locations on the substrate, allowing heat to conduct vertically through dedicated thermal paths rather than laterally through congested wiring areas, thus reducing heat generation per wire while maintaining wiring simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses temperature rises in semiconductor elements by increasing the bonding area of metal wires and improving heat radiation properties, enabling downsizing and high-density parallelization without compromising performance.
Implementation Method 1
the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material
Implementation Method 2
the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element
Implementation Method 3
the heat radiation efficiency is improved
Data Source
AI summary
An object is to suppress the temperature rise of a semiconductor element due to the heat generation of a metal wire. A semiconductor device includes a printed circuit board including a first circuit pattern and a second circuit pattern, and a semiconductor element arranged on an upper surface of the first circuit pattern, in which, in the semiconductor element, a drain electrode is arranged on an upper surface thereof and a gate electrode and a source electrode are arranged on a lower surface thereof, the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element.