Vertical Semiconductor Device Thinned Substrate Thermal Management
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Solution Overview
Problem
Semiconductor power devices, particularly VDMOS structures, face limitations due to high parasitic capacitance, poor thermal performance, and the inability to independently bias source and body regions, which affect their switching speed and heat dissipation capabilities.
Innovation Solution
The solution involves thinning the semiconductor substrate, decoupling the channel area from internal capacitance, and using trench isolation to reduce parasitic capacitance and thermal resistance, allowing for independent biasing of source and body regions, and integrating multiple vertical power devices on a single IC chip without common drains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the semiconductor substrate is thinned, then thermal resistance is reduced and heat dissipation is improved, but mechanical strength and wafer handling reliability deteriorate
Solution Approach 1:
The device structure is segmented into multiple functional layers including a first semiconductor layer, a second semiconductor layer, and an insulating layer. This segmentation allows the thin second semiconductor layer to provide low thermal resistance while the overall layered structure maintains mechanical integrity through the supporting first semiconductor layer.
Solution Approach 2:
The patent employs a composite structure combining different semiconductor layers with an insulating layer (such as silicon dioxide or silicon nitride). This composite approach enables the thin semiconductor layer to function effectively for heat dissipation while the insulating layer and thicker first semiconductor layer provide mechanical support and prevent wafer breakage.
2Speed
If trench isolation is used to reduce parasitic capacitance, then switching speed is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The device is divided into discrete regions separated by trenches filled with insulating material. This segmentation isolates adjacent devices and reduces parasitic capacitance between them, enabling faster switching speeds while maintaining a systematic manufacturing approach.
Solution Approach 2:
An insulating layer (intermediary material) is introduced into the trenches to electrically isolate adjacent semiconductor structures. This intermediary reduces parasitic capacitance without requiring complex device designs, as the isolation is achieved through the simple addition of dielectric material in the trench regions.
3Object-generated harmful factors
If the channel area is decoupled from internal capacitance, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The channel area is extracted from the bulk semiconductor substrate and formed as a separate thin layer. This extraction decouples the channel from the high-capacitance bulk substrate, reducing parasitic capacitance. The thin layer can be precisely controlled through established thin-film deposition and etching techniques.
Solution Approach 2:
The channel structure transitions from a three-dimensional bulk region to a thin two-dimensional layer. This dimensional change reduces the volume of the channel region, thereby reducing the associated parasitic capacitance while maintaining the necessary current conduction path through the thin layer.
4Adaptability or versatility
If multiple vertical power devices are integrated on a single IC chip without common drains, then device versatility and performance are improved, but device complexity and area requirements increase
Solution Approach 1:
Multiple vertical power devices are segmented and arranged in a compact array on the chip. Each device is isolated by trenches, allowing independent operation without common drain connections. This segmentation enables high device versatility while maintaining compact footprint through efficient spatial arrangement.
Solution Approach 2:
Multiple devices share common structural elements such as the insulating layer, trench isolation structures, and substrate infrastructure. This merging of common components reduces the total area required compared to fully discrete devices, while still allowing independent biasing and operation of each vertical power device.
Data Source
AI summary
A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.