Vertical Compound Semiconductor Vias for Higher 3D IC Density

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Solution Overview

Problem

Conventional 3D IC integration technologies face limitations in integration density due to the lateral extension of device structures and wiring, which restricts the packing density and switching velocity of three-dimensional integrated devices.

Innovation Solution

A vertical compound semiconductor structure is developed, featuring a substrate with a vertical channel opening and a layer stack comprising an electrically conductive layer and a compound semiconductor layer, allowing for increased integration density by integrating semiconductor device structures within the vertical vias, using materials like monocrystalline transition metal dichalcogenides such as MoS2, which can be deposited or formed through chemical conversion without damaging underlying layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional 3D IC integration technology is used with through silicon vias, then vertical connections between devices are achieved, but integration density is limited due to lateral extension of device structures and wiring

Engineering Contradiction:

Improveintegration densityVSAvoidlateral extension of device structures

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from planar 2D device structures to vertical 3D structures by integrating compound semiconductor layers within through-silicon-via channel openings. This dimensional change allows devices to be stacked vertically rather than arranged laterally, significantly increasing integration density while reducing the lateral footprint of the device structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests compound semiconductor device structures within the through-silicon-via channel openings. The vertical channel opening acts as a container that holds multiple functional layers (conductive layer, compound semiconductor layer, insulating layer), effectively placing one structure inside another to maximize space utilization and integration density.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If conventional silicon-based materials are used in vertical vias, then process compatibility is maintained, but integration density and switching velocity are limited

Engineering Contradiction:

Improveintegration densityVSAvoidprocess compatibility

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent employs compound semiconductor materials (such as III-V族 compounds like GaAs, InP, or their alloys) as composite material systems within the through-silicon-via structure. These compound semiconductor layers are integrated with silicon substrate and conductive layers to form a composite structure that combines the advantages of silicon processing compatibility with the superior electronic properties of compound semiconductors, enabling higher integration density and switching velocity.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent applies different materials with specific properties to different regions: silicon substrate for mechanical support and processing compatibility, compound semiconductor layers within the channel opening for high-performance device functionality, and conductive/insulating layers for electrical isolation and connection. This local differentiation of material properties optimizes both manufacturing ease and device performance.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly enhances integration density by enabling the integration of compound semiconductor layers within vertical channel openings, allowing for both mechanical and electrical connections, thereby overcoming the limitations of conventional 3D systems and achieving higher packing densities and switching velocities.

Implementation Method 1

using materials like monocrystalline transition metal dichalcogenides such as MoS2, which can be deposited or formed through chemical conversion without damaging underlying layers

Methodology Applied

Scientific EffectChemical conversion:

Data Source

PatentUS12166073B2Vertical semiconductor diode or transistor device having at least one compound semiconductor and a three-dimensional electronic semiconductor device comprising at least one vertical compound structure

Publication Date: 2024.12.10 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EV

AI summary

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.