Vertical Power Semiconductor Backside Process for Clean Wafer Removal
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Solution Overview
Problem
Existing methods for producing vertical power semiconductor components on silicon wafers face challenges in completely removing the silicon wafer to ensure vertical current flow, leading to inefficiencies and potential contamination.
Innovation Solution
A method involving applying a silicon wafer to a subcarrier wafer, grinding and dry etching the wafer to a specific thickness, ion implantation in the drift layer with high dopant concentration, and generating an ohmic contact with a metal layer, followed by complete removal of the subcarrier wafer, stabilizing the process with a glass or silicon subcarrier and using selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the silicon wafer is removed after processing the front side to ensure vertical current flow, then the current flow is ensured, but the removal process is incomplete and leads to contamination
Solution Approach 1:
The silicon wafer removal process is divided into multiple stages: first grinding the wafer to a specific thickness, then dry etching to create a porous layer, followed by selective wet etching that targets the porous silicon while leaving the gallium nitride layers intact. This segmentation allows complete removal without contamination of the remaining semiconductor layers.
Solution Approach 2:
A porous silicon intermediate layer is created through dry etching before final removal. This porous layer acts as an intermediary that facilitates selective etching - it allows the wet etchant to penetrate and remove the silicon wafer completely while the dense gallium nitride layers resist the etchant, preventing contamination.
2Reliability
If ion implantation with high dopant concentration is applied to the drift layer, then the contact resistance is reduced, but the process complexity increases
Solution Approach 1:
The ion implantation process changes key parameters: dopant concentration is increased to greater than 1e19 cm^-3, and silicon-containing dopants are used specifically. These parameter changes create a highly conductive contact semiconductor layer that reduces contact resistance effectively.
3Ease of manufacture
If the silicon wafer is ground to a specific thickness before etching, then the etching process becomes simpler and more selective, but the additional grinding step increases process complexity
Solution Approach 1:
The silicon wafer is ground to a specific thickness (100-500 μm) before etching as a preliminary action. This pre-processing step creates optimal conditions for the subsequent dry etching process, enabling better selectivity and control during etching of the porous silicon layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures complete removal of the silicon wafer, reduces resistance in the contact semiconductor layer, and is cost-effective, providing a stable and contamination-free process for producing vertical power semiconductor components.
Implementation Method 1
grinding the silicon wafer to a specific thickness
Implementation Method 2
dry etching the silicon wafer
Implementation Method 3
implanting ions into the drift layer, wherein a contact semiconductor layer is formed
Implementation Method 4
the buffer layer is etched wet-chemically or by means of a chlorine-based dry-etching process
Data Source
AI summary
A method for producing vertical power semiconductor components. The method includes: applying a first side of a silicon wafer onto a subcarrier wafer, wherein a front side of the vertical power semiconductor components is arranged on the first side of the silicon wafer and the front side of the vertical power semiconductor components comprises a buffer layer and a drift layer; grinding the silicon wafer to a specific thickness; dry etching the silicon wafer; etching the buffer layer; implanting ions into the drift layer, wherein a contact semiconductor layer is formed; generating an ohmic contact by applying a metal layer onto the contact semiconductor layer; and removing the subcarrier wafer.