Vertical Surround Gate Transistor SRAM Cell Area Reduction
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Solution Overview
Problem
Conventional SRAM cells using SGTs face limitations in reducing cell area due to the width of diffusion layers and distances between them, hindering the achievement of smaller cell sizes for high-capacity SRAMs in LSIs.
Innovation Solution
The semiconductor memory device employs a static memory cell composed of four MOS transistors and two load resistance elements, arranged in a vertical hierarchical structure with shared diffusion layers and gate connections, allowing for a more efficient use of space and reduced cell area by using contact plugs and shared contacts for load resistance elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistors are used in SRAM cells, then the transistor structure is simple to manufacture, but the cell area becomes large limiting integration density
Solution Approach 1:
The patent transitions from planar transistors to surrounding gate transistors (SGTs) with vertical columnar semiconductor layers. The gate electrode surrounds the columnar layer in a cylindrical configuration, changing the transistor architecture from two-dimensional planar to three-dimensional vertical structure. This dimensional change reduces the footprint area while maintaining transistor functionality, directly resolving the contradiction between manufacturing simplicity and cell area reduction.
2Reliability
If diffusion layer width and spacing are increased for reliable transistor operation, then device reliability improves, but cell area increases reducing integration capacity
Solution Approach 1:
The surrounding gate transistor structure extends the gate control into the vertical dimension by wrapping it around the columnar semiconductor layer. This provides enhanced gate control over the channel without requiring larger lateral diffusion layer dimensions. The vertical gate structure achieves reliable transistor operation with smaller lateral footprint, resolving the contradiction between reliability and area.
Solution Approach 2:
The patent merges the source and drain diffusion layers into a single continuous diffusion layer that extends beneath both columnar semiconductor layers. This merging reduces the number of discrete diffusion regions and minimizes the lateral space required, while the vertical columnar structure maintains proper electrical isolation and transistor functionality, achieving reliability with reduced area.
3Adaptability or versatility
If more diffusion layers are used to form four separate transistors, then transistor functionality is ensured, but manufacturing complexity and area increase
Solution Approach 1:
The patent combines the source and drain diffusion regions into a single shared diffusion layer that serves both transistors. Instead of using four separate diffusion layers for source and drain of each transistor, the merged structure uses one continuous diffusion layer with two vertical columnar semiconductor layers extending from it. This reduces diffusion layer complexity while maintaining complete transistor functionality through the vertical SGT architecture.
Solution Approach 2:
The single shared diffusion layer performs multiple functions: it serves as the source for one transistor, the drain for the other transistor, and provides a common electrical connection point. The vertical columnar semiconductor layers also serve dual purposes as both source and drain regions for their respective transistors. This multi-functionality reduces the number of discrete components needed while ensuring complete transistor functionality.
Data Source
AI summary
In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers serve as memory nodes. The drain, gate and source of the MOS transistors are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area.