Vertical SiC MOSFET With Intermediate Layer
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Solution Overview
Problem
Conventional SiC MOSFETs face challenges in achieving high short-circuit strength and limiting gate oxide field strength while maintaining low on-state resistance, as these parameters are typically correlated, and existing designs struggle to independently optimize them, leading to reduced component reliability and increased power loss.
Innovation Solution
A vertical SiC MOSFET design featuring an epitaxial layer with a horizontally extending intermediate layer of opposing doping, which acts as a junction field effect transistor to limit current during short circuits and shield the gate oxide, allowing for independent optimization of short-circuit strength and on-state resistance without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Rdson is decreased to reduce power loss, then on-state resistance is improved, but short-circuit strength is reduced
Solution Approach 1:
The drift region is segmented into multiple regions with different doping concentrations (first doping concentration in the upper part, second doping concentration in the lower part). This segmentation allows the upper region to contribute to low on-state resistance while the lower region provides enhanced short-circuit strength, resolving the contradiction between power loss and short-circuit strength.
Solution Approach 2:
Different regions of the drift region are assigned different doping concentrations to fulfill different functions. The first doping concentration region optimizes for low on-state resistance (reducing power loss), while the second doping concentration region optimizes for high short-circuit strength. This local differentiation allows simultaneous optimization of both parameters.
2Reliability
If gate oxide field strength is limited to protect the gate, then gate reliability is improved, but current conduction capability is reduced
Solution Approach 1:
The intermediate layer with opposite doping type acts as a mediator between the gate oxide and the drift region. It provides electrostatic shielding that limits the maximum field strength at the gate oxide interface to below 3 MV/cm, protecting the gate while still allowing sufficient current conduction through the MOS channel. The intermediate layer decouples the gate field limitation from the current conduction capability.
3Loss of energy
If conventional MOSFET structure is used to achieve low Rdson, then on-state resistance is improved, but short-circuit robustness is insufficient
Solution Approach 1:
The drift region is divided into multiple doped regions with different concentrations, creating a segmented structure that provides both low on-state resistance and high short-circuit robustness. The segmentation allows different regions to contribute differently to the overall device performance during normal operation versus short-circuit conditions.
Solution Approach 2:
The invention extends the conventional planar MOSFET structure by adding depth differentiation through multiple doped regions in the drift region and an intermediate layer. This vertical dimensionality addition allows independent optimization of on-state resistance (controlled by overall doping) and short-circuit robustness (controlled by the intermediate layer and doping profile distribution).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high short-circuit robustness, limits gate oxide field strength below 3 MV/cm, reduces on-state resistance, and enhances component reliability by effectively shielding the MOS channel and reducing short-channel effects, enabling a controlled adjustment of MOSFET properties through doping and dimensioning.
Implementation Method 1
an oppositely doped compensation layer allowing the maximum field strengths that occur to be limited
Implementation Method 2
acts as a junction field effect transistor to limit current during short circuits
Implementation Method 3
limits the gate field strength (see e.g. Kevin Matocha, 'Challenges in SiC Power MOSFET Design,' Solid State Electronics 52 (2008) 1631-1635
Implementation Method 4
enhances component reliability by effectively shielding the MOS channel and reducing short-channel effects
Data Source
AI summary
A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.