Vertical-Sidewall SAGE Endcaps for Tighter Diffusion Spacing
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices poses challenges due to constraints on lithographic processes, leading to a trade-off between feature dimension and spacing, and existing self-aligned gate endcap (SAGE) architectures face issues with shadowing and metal remnants during etch processes.
Innovation Solution
The implementation of self-aligned gate endcap (SAGE) architectures with vertical sidewalls, achieved through sidewall slope engineering of thermally grown oxide spacers, allows for tunable self-aligned wall profiles and reduces the need for lithographic patterning, thereby improving layout density and diffusion spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic patterning is used to pattern semiconductor features, then feature dimensions can be controlled, but spacing between features must be increased to avoid patterning constraints
Solution Approach 1:
The patent applies preliminary action by forming sacrificial mandrels and spacers before the final gate patterning step. The mandrels are deposited and patterned first, then spacers are formed around them, and finally the mandrels are removed to create the gate structure. This sequence allows the gate spacing to be defined by the mandrel spacing rather than direct lithographic patterning of the gates themselves, enabling tighter spacing.
Solution Approach 2:
The patent uses sacrificial mandrels as intermediary structures that mediate between the lithographic patterning step and the final gate structure. The mandrels serve as temporary placeholders that define the spacing, allowing the actual gates to be formed indirectly through spacer deposition and mandrel removal, thus bypassing lithographic spacing constraints.
2Area of stationary object
If self-aligned gate endcap structures are formed with sloped sidewalls, then layout density can be improved, but shadowing and metal remnants occur during etch processes
Solution Approach 1:
The patent applies parameter changes by modifying the sidewall angle parameter of the gate endcap structures. Instead of using sloped sidewalls that cause shadowing, the invention forms structures with substantially vertical sidewalls (angles between 80-90 degrees). This parameter change eliminates the shadowing effect during etching while maintaining the self-aligned geometry for high layout density.
Solution Approach 2:
The patent replaces the mechanical shadowing effect caused by sloped sidewalls with a vertical sidewall configuration. The vertical geometry substitution eliminates the progressive shadowing that occurs during directional etching, preventing metal remnants from forming in the shadowed regions while preserving the space-saving self-aligned structure.
3Productivity
If diffusion spacing is reduced to increase device density, then more devices can be packed, but device-to-device variability in electrical parameters increases
Solution Approach 1:
The patent applies self-service through self-aligned structures where the gate endcaps automatically define the diffusion regions' positions and dimensions. The spacers form conformally around the mandrels, and the mandrel removal creates precisely defined gaps that become the diffusion regions. This self-aligned process eliminates the need for separate alignment steps, ensuring consistent spacing and reducing variability even at reduced diffusion spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more aggressive scaling of diffusion to diffusion spacing, reduces device-to-device variability in electrical parameters, and avoids issues like metal remnants and shadowing, thereby enhancing the performance and density of semiconductor devices.
Implementation Method 1
sidewall slope engineering of thermally grown oxide spacers
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.