Vertical Silicon Transistor Structure for Short-Channel Miniaturization
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Solution Overview
Problem
Existing transistors are limited in miniaturization, electrical characteristics, and area occupancy, hindering the development of high-resolution display devices for applications like virtual and augmented reality.
Innovation Solution
A semiconductor device structure comprising specific layers and materials, including conductive and semiconductor layers with controlled impurity elements, allows for a vertical field-effect transistor (VFET) design with a short channel length and reduced area occupancy, utilizing amorphous or polycrystalline silicon and hydrogen-containing insulating layers for improved reliability and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional transistor structures are used, then manufacturing is simpler, but miniaturization is limited and area occupancy is large
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical field-effect transistor (VFET) structure, utilizing the vertical dimension to achieve miniaturization. The gate electrode is positioned vertically above the semiconductor layer, creating a vertical channel that significantly reduces the footprint area while maintaining effective channel length for current control.
Solution Approach 2:
The patent employs multiple nested layers including the gate insulating layer surrounding the gate electrode, the semiconductor layer forming the channel, and various insulating layers (first and second insulating layers) enclosing the structure. This nested arrangement achieves compact packaging and reduced area occupancy.
2Length of moving object
If transistor channel length is reduced for miniaturization, then area is reduced, but electrical characteristics deteriorate
Solution Approach 1:
The patent carefully controls the thickness parameters of the gate insulating layer and semiconductor layer to maintain optimal electrical characteristics. The gate insulating layer thickness is set to 50-200 nm and the semiconductor layer thickness to 50-300 nm, ensuring sufficient gate control while preventing short-channel effects and maintaining reliable transistor operation.
Solution Approach 2:
The patent uses composite material structures including the combination of the gate insulating layer (first insulating layer) and the semiconductor layer, where the interface between these materials is optimized to ensure good electrical characteristics. The specific material composition and interface quality are controlled to maintain reliability in miniaturized structures.
3Manufacturing precision
If high-resolution display is achieved, then pixel density increases, but manufacturing cost increases due to expensive equipment requirements
Solution Approach 1:
The patent employs self-aligned manufacturing processes where the vertical structure and layer stacking automatically provide alignment for subsequent processing steps. The gate electrode, gate insulating layer, and semiconductor layer are formed in a self-aligned manner, reducing the need for complex alignment equipment and lowering manufacturing costs while achieving high resolution.
Data Source
AI summary
A transistor that can be miniaturized is provided. A transistor having favorable electrical characteristics is provided. A semiconductor device includes a first to a third conductive layer, a first to a third semiconductor layer, and a first and a second insulating layer. The second semiconductor layer is provided over the first conductive layer, the first insulating layer is provided over the second semiconductor layer, the second conductive layer is provided over the first insulating layer, and the third semiconductor layer is provided over the second conductive layer. The first insulating layer includes an opening reaching the second semiconductor layer. The first semiconductor layer includes a portion in contact with the third semiconductor layer, a portion in contact with a side surface of the first insulating layer inside the opening, and a portion in contact with the second semiconductor layer. The second insulating layer covers the first semiconductor layer. The third conductive layer overlaps with the first semiconductor layer with the second insulating layer therebetween. The first to the third semiconductor layer contain silicon. The second and the third semiconductor layer contain the same impurity element. The first insulating layer contains hydrogen, nitrogen, and silicon.