Vertical SMD Bridge in Leadframe Packages for Low Impedance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing solutions for integrating passive electrical components into semiconductor packages suffer from poor electrical performance due to long connection formations, which can lead to increased impedance, especially above 30 MHz.

Innovation Solution

A semiconductor device and manufacturing method where a two-terminal surface-mount device (SMD) is mounted vertically on a die-pad and coupled to a leadframe, with an elongate electrical component bridge-like between the lead and the pad, using electrically-conductive masses and wire bonding to reduce impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If passive electrical components are integrated into semiconductor packages using conventional connection formations, then component integration is achieved, but electrical performance deteriorates due to increased impedance from long connection paths

Engineering Contradiction:
Improvecomponent integrationVSAvoidelectrical performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent transitions from planar (2D) connection formations to three-dimensional (3D) vertical stacking. The SMD component is mounted vertically on the die-pad with its terminals extending in the vertical dimension, creating a bridge-like structure that directly connects to leadframe leads. This dimensional change dramatically shortens the electrical connection path and reduces impedance, achieving up to 40% impedance reduction above 30 MHz while maintaining component integration capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If long connection formations are used to couple electrical components to integrated circuits, then component mounting flexibility is improved, but impedance increases especially above 30 MHz

Engineering Contradiction:
Improvemounting flexibilityVSAvoidimpedance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The invention introduces vertical stacking in the third dimension, mounting the SMD component vertically on the die-pad rather than in the planar plane. This vertical orientation creates direct electrical pathways through the vertical dimension, dramatically reducing connection length and impedance while preserving mounting flexibility through the bridge-like configuration that can accommodate various component types and orientations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Area of stationary object

If conventional planar mounting is used for SMD components, then PCB space utilization is optimized, but electrical connection length increases leading to higher impedance

Engineering Contradiction:
ImprovePCB spaceVSAvoidelectrical connection quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent moves component mounting from the horizontal plane to the vertical dimension by stacking the SMD component vertically on the die-pad. This vertical arrangement maintains compact footprint on the PCB surface while creating direct, short electrical connections through the vertical stack. The bridge-like structure extends vertically to connect the SMD terminals directly to the leadframe leads, minimizing connection length and impedance without sacrificing space efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11764134B2Semiconductor device including electrical component connecting a semiconductor chip to a leadframe and a corresponding method of manufacture
Publication Date: 2023.09.19 STMICROELECTRONICS SRL
  • US11764134B2 patent drawing
  • US11764134B2 patent drawing
  • US11764134B2 patent drawing

AI summary

A semiconductor chip is mounted to a chip mounting portion of a leadframe which further includes and one or more leads in the leadframe arranged facing the chip mounting portion. The lead lies in a first plane and the chip mounting portion lies in a second plane, the first plane and the second plane mutually offset with a gap therebetween. An electrical component (such as a capacitor) is arranged on the chip mounting portion and extends vertically between the first plane and the second plane.