Vertical SMT Package Layout for Small RF Module Footprints

The patent transitions from two-dimensional planar configurations to three-dimensional vertical stacking by positioning conductive plates at different heights (z-dimension) within the encapsulant. Multiple conductive plates are stacked vertically with dielectric material between them, allowing increased capacitance and inductance without increasing lateral footprint dimensions. This vertical arrangement enables maintaining high Q values while achieving small footprint sizes.

The patent implements nested structures where conductive plates and dielectric layers are stacked within each other in a compact vertical arrangement. The conductive plates are positioned between dielectric material layers, creating a nested configuration that maximizes the use of vertical space. This nesting allows multiple functional elements to be contained within a small lateral footprint while maintaining their electrical performance.

The patent divides the capacitor or inductor into multiple discrete conductive plates and dielectric layers stacked vertically. Each plate and dielectric layer can be manufactured separately using standard PCB fabrication processes, then assembled through co-firing or other joining techniques. This segmentation allows for modular manufacturing, improving yield and reducing costs compared to attempting to miniaturize single-layer structures.

The patent changes the geometric parameters of the conductive plates and dielectric layers to optimize both performance and manufacturability. By adjusting plate dimensions, spacing, and material properties, the design achieves high Q values in small footprints using conventional manufacturing processes. The vertical stacking parameter allows standard fabrication techniques to be applied without requiring advanced miniaturization processes.