Vertical SMT Package Layout for High-Q RF Components

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Solution Overview

Problem

Existing surface-mount technology (SMT) devices face challenges in reducing their footprint while maintaining performance, particularly in radio-frequency (RF) applications, where components need to be smaller without compromising quality factor (Q) values, capacitance, or inductance.

Innovation Solution

The SMT device design incorporates a body with a rectangular cuboid shape, where the height is greater than the width, allowing for thicker dielectric layers, increased numbers of conductive plates, and thicker conductive plates, which enhance capacitance, inductance, and Q values without increasing the overall module height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the lateral dimensions of SMT devices are reduced, then the footprint area is decreased, but the capacitance, inductance, and quality factor (Q) values deteriorate

Engineering Contradiction:
Improvefootprint areaVSAvoidperformance metrics (capacitance, inductance, Q values)
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from traditional planar configurations to a three-dimensional stacked architecture where multiple conductive plates are arranged in vertical layers separated by dielectric materials. This vertical stacking enables increased capacitance and inductance values without expanding the lateral footprint, as the electrical properties are enhanced through the third dimension (height) rather than through lateral expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention employs composite structures combining multiple dielectric materials with different permittivity values and multiple conductive plate materials in a stacked configuration. By strategically selecting and arranging materials with varying electrical properties, the design achieves enhanced capacitance and inductance performance within a compact footprint, resolving the contradiction between size reduction and performance maintenance.

Inventive Principle:
Principle #40Composite materials

2Reliability

If thicker dielectric layers are implemented, then the breakdown voltage increases, but the overall device height increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoiddevice height
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent utilizes composite dielectric structures where multiple layers of dielectric materials with different thicknesses and permittivity values are stacked between conductive plates. This composite approach allows optimization of the electric field distribution across the voltage stress path, achieving high breakdown voltage ratings while maintaining a compact overall height through efficient material selection and layer configuration.

Inventive Principle:
Principle #40Composite materials

3Reliability

If the number of conductive plates is increased, then the capacitance increases, but the device complexity increases

Engineering Contradiction:
ImprovecapacitanceVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The capacitor structure is segmented into multiple discrete conductive plates separated by dielectric layers, with each plate pair contributing to the total capacitance. This segmentation allows the total capacitance to be achieved through the series/parallel combination of multiple smaller capacitor units, facilitating modular manufacturing and assembly while achieving high capacitance values without excessive structural complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enables a reduction in lateral dimensions of SMT devices while maintaining or improving performance metrics such as capacitance, inductance, and quality factor (Q), thus addressing the need for smaller RF modules without sacrificing performance.

Implementation Method 1

thicker dielectric layers between the conductive plates. The thicker dielectric layers can result in an increased breakdown voltage of the capacitor

Methodology Applied
Scientific EffectDielectric polarization: Dielectric

Implementation Method 2

The increased number of conductive plates can result in an increased capacitance of the capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 3

The increased number of turns of the conductive traces can result in an increased inductance of the inductor

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Data Source

PatentUS20250070814A1Packaged electrical devices and related methods
Publication Date: 2025.02.27 SKYWORKS SOLUTIONS INC
  • US20250070814A1 patent drawing
  • US20250070814A1 patent drawing
  • US20250070814A1 patent drawing

AI summary

A method for fabricating a surface-mountable device can include forming or providing an electrical element, and forming a body to support the electrical element, such that the body has a rectangular cuboid shape with a length, a width, and a height that is greater than the width. The body can include a base plane configured to allow surface mounting of the device. The method can further include forming first and second terminals on the base plane, such that the first and second terminals are electrically connected to the electrical element.