Vertical SoC-PMIC Stack With Thin-Film Inductors for Low-Noise Power
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Solution Overview
Problem
Conductive wires on the main logic board introduce parasitic effects and electrical noise that compromise the performance of system-on-chip (SoC) devices by causing voltage drops and degrading signal quality.
Innovation Solution
The integration of a power management integrated circuit (PMIC) and SoC in a vertical stack with thin film inductors between them, reducing the need for conductive wires and minimizing parasitic effects by using a package substrate with via interconnects to electrically couple the PMIC and SoC, and incorporating thin film inductors to manage power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive wires are used to connect PMIC and SoC on the main logic board, then electrical connection is established, but parasitic effects and electrical noise are introduced
Solution Approach 1:
The patent transitions from a planar connection architecture to a three-dimensional vertical stack architecture. The PMIC and SoC are connected vertically through via interconnects in the package substrate, eliminating the need for long horizontal conductive wires on the logic board. This dimensional change dramatically reduces parasitic resistance and inductance while minimizing electrical noise coupling.
Solution Approach 2:
The patent merges the PMIC and SoC into a single vertical package structure with integrated interconnects. The package substrate with via interconnects combines multiple functions: mechanical support, electrical connection, and signal routing. This integration eliminates separate conductive wire connections and reduces the overall connection path, thereby reducing parasitic effects.
2Power
If conductive wires are routed on the main logic board, then power delivery is achieved, but voltage drop occurs due to parasitic resistance
Solution Approach 1:
The vertical via interconnect architecture replaces horizontal wire routing, creating a direct vertical path for power delivery from PMIC to SoC. This three-dimensional connection path is significantly shorter than planar wire routing, dramatically reducing parasitic resistance and associated voltage drops while maintaining full power delivery capability.
Solution Approach 2:
The package substrate with via interconnects acts as an intermediary structure that provides low-resistance electrical paths between PMIC and SoC. The via interconnects serve as optimized mediators for power and signal transmission, replacing high-parasitic conductive wires with vertically-integrated low-inductance connections.
3Reliability
If PMIC and SoC are integrated in a vertical stack, then parasitic effects are reduced, but device complexity increases
Solution Approach 1:
The package substrate integrates multiple functions into a single component: mechanical support for both dies, electrical interconnects via vertical vias, and signal routing paths. This functional merging reduces the number of separate components and connections needed, simplifying the overall system despite the vertical integration architecture.
Solution Approach 2:
The package substrate serves multiple purposes simultaneously: it provides mechanical support for the PMIC and SoC dies, establishes electrical connections through via interconnects, routes signals between components, and provides structural protection. This multi-functionality reduces the need for additional specialized components, offsetting the complexity of vertical integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces parasitic resistance and capacitance, enhancing the quality of the DC power supply to the SoC, thereby improving performance by minimizing noise and voltage drops.
Implementation Method 1
the thin film inductor is configured to provide a magnetic field in the first and second stacks of magnetic layers in response to a current passing through the conductive wire
Implementation Method 2
a first stack of magnetic layers and a second stack of magnetic layers. The conductive wire is disposed between the first and second stacks of magnetic layers
Data Source
AI summary
A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.