Vertical SOI Channel Fabrication for DRAM Refresh and Speed
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Solution Overview
Problem
Conventional semiconductor device fabrication methods result in increased channel resistance and decreased read/write speed characteristics due to the enlargement of the total gate channel length, leading to unfavorable refresh characteristics in DRAM devices.
Innovation Solution
The method involves forming a vertical SOI channel region by etching the lower part of the sidewalls of the active region and forming a portion of the storage node junction region over a device isolation structure, which reduces leakage current and improves the refresh characteristic by maintaining a low electric field and increasing the driving current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of a cell transistor is decreased to increase speed, then the read/write speed characteristics are improved, but the ion concentration in the channel region must be increased to maintain threshold voltage, which enhances the electric field in source/drain regions and increases leakage current, degrading the refresh characteristic
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess in the active region and creating a vertical channel region that extends downward. This three-dimensional channel structure allows the channel to be positioned below the bit line junction, separating the channel region from the high-field source/drain regions. The vertical channel maintains adequate threshold voltage through its depth while reducing the horizontal channel length for faster operation, and isolates it from leakage-prone regions.
Solution Approach 2:
The patent segments the channel region from the source/drain regions by positioning the vertical channel below the bit line junction level. The channel is divided into distinct regions: a vertical channel portion extending downward from the surface, and a horizontal channel portion at the bottom. This segmentation allows independent optimization of channel length for speed while maintaining threshold voltage through controlled ion implantation in the channel region, separate from the source/drain doping that causes leakage.
2Reliability
If the total gate channel length is enlarged to maintain threshold voltage, then the threshold voltage is maintained, but the channel resistance increases, decreasing the read/write speed characteristics
Solution Approach 1:
The patent transitions from a planar channel to a vertical channel structure by forming a recess and growing or implanting semiconductor material to create a channel extending downward. This vertical configuration increases the effective channel length for threshold voltage control without increasing the horizontal projection, thus maintaining fast read/write speeds. The channel depth provides additional degrees of freedom for voltage control independent of channel width.
Solution Approach 2:
The patent changes the geometric parameters of the channel by creating a vertical structure with controlled depth and width. The channel length is effectively increased in the vertical direction while the horizontal dimensions remain small. Ion implantation parameters are adjusted to provide appropriate doping concentration in the vertical channel region, maintaining threshold voltage without requiring excessive channel length that would increase resistance.
3Reliability
If the etching rate near the device isolation structure is slower, then the device isolation structure integrity is maintained, but a silicon horn is formed at the semiconductor substrate near the device isolation structure, complicating the fabrication process
Solution Approach 1:
The patent performs preliminary actions by forming the recess and vertical channel structure before completing the device isolation structure formation. The recess is etched into the substrate, and the vertical channel is formed, and only then is the device isolation structure formed to fill and planarize the surface. This sequence prevents etching rate variations from causing silicon horn formation, as the critical channel regions are already defined and protected.
Solution Approach 2:
The patent segments the fabrication process into distinct stages: first forming the recess and vertical channel in the substrate, then separately forming the device isolation structure. This segmentation allows the etching process to be optimized for vertical channel formation without concern for device isolation integrity, and the device isolation can be formed subsequently to fill any remaining variations, eliminating the silicon horn problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the read/write speed characteristics and refresh performance of the semiconductor device by reducing channel resistance and maintaining a low electric field, thereby improving the driving current and threshold voltage characteristics.
Implementation Method 1
a lower part of sidewalls of an active region where a storage node junction region is to be formed is etched
Data Source
AI summary
A method for fabricating a semiconductor device, including (a) etching a semiconductor substrate to form a first trench defining an active region; (b) forming a first spacer on sidewalls of the first trench; (c) etching a bottom of the first trench to form a second trench; (d) etching a sidewall of the second trench to form a third trench including an undercut space; (e) forming a device isolation structure that fills the first, second and third trenches; (f) etching the semiconductor substrate of a gate region to form a recess; and (g) forming a gate that fills the recess.