Vertical SOI Channel Structures for DRAM Leakage Reduction
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Solution Overview
Problem
The reduction in channel length of cell transistors in semiconductor devices increases ion concentration, leading to enhanced electric fields in source/drain regions, which degrades the refresh characteristics of dynamic random access memory (DRAM) structures by increasing leakage current.
Innovation Solution
A recess channel region with vertical silicon-on-insulator (SOI) channel structures is formed at the sidewalls of device isolation structures under the gate, increasing the channel area and reducing leakage current, thereby improving the short channel effect and refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length of cell transistor is decreased, then the ion concentration of cell channel region is increased to maintain threshold voltage, but the electric field in source/drain regions is enhanced which increases leakage current and degrades refresh characteristics
Solution Approach 1:
The patent transitions from a planar channel structure to a vertical channel structure by forming recesses in the semiconductor substrate and growing epitaxial layers that extend vertically. This dimensional change allows the channel to extend in the vertical direction rather than only horizontally, increasing the effective channel area without requiring further reduction in horizontal channel length, thereby maintaining threshold voltage while reducing the horizontal electric field that causes leakage current
Solution Approach 2:
The channel region is segmented into multiple vertical channels formed in separate recesses within the semiconductor substrate. Each recess contains its own vertical channel structure, allowing the total channel area to be increased by adding more segmented channels rather than enlarging a single channel, which helps maintain threshold voltage while distributing the electric field across multiple independent channels
2Productivity
If the channel length is decreased to improve device scaling, then manufacturing precision and control become more difficult
Solution Approach 1:
By moving the channel structure to the vertical dimension, the patent achieves device scaling in the horizontal plane without proportionally reducing the controllable channel dimensions. The vertical channel length can be precisely controlled through epitaxial growth parameters, providing better manufacturing precision while maintaining scaled-down horizontal footprints for improved productivity
3Area of stationary object
If vertical SOI channel structures are formed at sidewalls of device isolation structures, then channel area is increased and leakage current is decreased, but device structure complexity is increased
Solution Approach 1:
The patent merges the channel-forming process with the device isolation structure formation by growing the vertical channel structures directly on the sidewalls of the isolation regions. This combining of functions reduces the need for separate channel formation steps and simplifies the overall device structure while still achieving increased channel area through the vertical sidewall configuration
Data Source
AI summary
The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region.