Vertical Trench SONOS Cell Integration in SOI CMOS
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Solution Overview
Problem
Conventional floating gate memories face integration challenges with CMOS due to high voltage requirements, limiting battery life and increasing costs, while planar SONOS cells struggle with scaling and integration on SOI substrates due to short channel lengths and separate gate construction needs.
Innovation Solution
A method for fabricating vertical trench SONOS cells in an SOI substrate, allowing for dense NVRAM integration by forming the trench early in the process flow, with a source diffusion beneath the trench, a select gate channel on the trench sides, and a silicided doped region adjacent to an outdiffused bridge, enabling 1F spacing between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional floating gate memory is used, then high voltage operation is achieved, but integration with CMOS is problematic and battery life is severely limited
Solution Approach 1:
The patent transitions from high-voltage floating gate operation to moderate-voltage SONOS operation by changing the memory mechanism parameters. SONOS cells operate at approximately 5V compared to 10V or higher for floating gate, enabling compatibility with standard CMOS power supplies and eliminating the need for separate high voltage supplies or charge-pumping circuits
Solution Approach 2:
The patent extracts the high voltage supply requirement from the memory operation by adopting SONOS technology that operates at moderate voltages. This removes the problematic dependency on separate high voltage power supplies and charge-pumping circuitry, allowing direct integration with standard CMOS logic
2Use of energy by moving object
If planar SONOS cells are used, then moderate operating voltages are achieved, but scaling is limited and cell sizes are large
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell layout to vertical three-dimensional trench structures. The vertical trench SONOS cells utilize the depth dimension by forming trenches through the substrate with memory gates and control gates positioned at different depths, achieving high-density integration while maintaining moderate operating voltages
Solution Approach 2:
The patent implements nested gate structures where the select gate channel is positioned within the vertical trench, and the memory gate is positioned within the trench as well, with the control gate electrode surrounding the memory gate. This nested arrangement maximizes space utilization and achieves high cell density
3Ease of manufacture
If planar SONOS cells are fabricated separately from CMOS process, then SONOS memory gate is created, but additional lithography masks are required and integration cost increases
Solution Approach 1:
The patent merges the SONOS memory gate fabrication with the CMOS processing sequence by forming both gates simultaneously using the same lithography and deposition steps. The select gate channel and memory gate are formed in the same process flow, eliminating the need for separate lithography masks and reducing integration complexity
Solution Approach 2:
The patent creates a universal processing sequence that serves both CMOS logic and SONOS memory fabrication. The same gate formation process produces functional gates for both CMOS devices and SONOS memory cells, making the process applicable to multiple device types without requiring separate specialized processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high-density NVRAM cells with SOI-based CMOS technology, reducing voltage requirements and eliminating the need for separate power supplies, thus enhancing battery life and simplifying integration while avoiding reliability issues associated with floating gate memories.
Implementation Method 1
vertical outdiffusing dopant from the Si-containing conductively filled recess to provide top and bottom outdiffused regions
Implementation Method 2
forming a silicided doped region in the top semiconductor layer adjacent to and in contact with the top outdiffused region
Data Source
AI summary
A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.