Vertical Source Contact Filling for Void-Free Semiconductor Stacks
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Solution Overview
Problem
Existing gap-filling processes for high aspect ratio structures in semiconductor devices often result in voids, which can compromise the reliability and performance of vertical semiconductor devices.
Innovation Solution
A method for fabricating a vertical semiconductor device that involves forming a multi-layer stack structure with a source layer and gate electrodes, creating a vertical structure with a channel layer insulated from the source layer, and using a combination of conductive layers with different dopants to form a source channel contact that fills high aspect ratio recesses without voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gap-fill process is performed in high aspect ratio structures, then the structure can be formed, but voids may occur compromising reliability
Solution Approach 1:
The patent changes the physical and chemical parameters of the filling material by using a low-viscosity precursor solution that can flow into high aspect ratio recesses, and controlling the dopant concentration and deposition parameters to ensure complete filling without voids, thereby resolving the contradiction between achieving complete gap-filling and maintaining device reliability
Solution Approach 2:
The patent employs composite material structures including multi-layer stack structures with alternating dielectric and sacrificial layers, and composite conductive layers with different dopants (phosphorus-doped and carbon-doped polysilicon) that work together to enable complete filling and form reliable source channel contacts without voids
2Manufacturing precision
If conductive layers with different dopants are used to fill high aspect ratio recesses, then void-free filling is achieved, but process complexity increases
Solution Approach 1:
The patent segments the conductive layer formation into multiple stages with different dopants - first forming a phosphorus-doped polysilicon layer, then forming a carbon-doped polysilicon layer. This segmentation allows each layer to be optimized for specific functions (filling and contact formation) and enables void-free filling while managing process complexity through systematic multi-step fabrication
Solution Approach 2:
The patent performs preliminary actions by first forming the multi-layer stack structure with sacrificial layers in place before forming the conductive layers. The sacrificial layers are removed after conductive layer formation, and seal spacers are formed to protect the structure. This preliminary structuring enables subsequent void-free filling while organizing the complex process into manageable sequential steps
Data Source
AI summary
A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.