Vertical Semiconductor Source Contact for Void-Free Gap Fill
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gap-fill processes for high aspect ratio structures in semiconductor devices often result in voids, compromising the reliability of vertical semiconductor devices.
Innovation Solution
A method for fabricating a vertical semiconductor device involving a multi-layer stack structure with a source layer, gate electrodes, and a vertical structure with a channel layer, where a horizontal source channel contact is formed using conductive layers with different dopants to prevent voids and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional gap-fill process is used for high aspect ratio structures, then the structure can be formed, but voids are created compromising device reliability
Solution Approach 1:
The conductive layer is divided into multiple segments with different dopants (first dopant and second dopant) creating distinct regions. This segmentation allows different portions of the high aspect ratio structure to be filled with materials having different wet etch rates, enabling complete void-free filling while maintaining structural integrity and device reliability.
Solution Approach 2:
Different regions of the conductive layer are assigned different dopant concentrations and types, creating local variations in wet etch rate. This local quality differentiation ensures that each region fills appropriately during the gap-fill process, preventing void formation in critical areas while maintaining overall device reliability.
2Manufacturing precision
If conductive layers with different dopants are used, then void-free filling is achieved, but process complexity increases
Solution Approach 1:
The conductive layer is formed with different dopants deposited in sequence during the fabrication process. By preliminarily establishing the multi-dopant structure before the gap-fill operation, the system ensures void-free filling is achieved while managing process complexity through integrated deposition steps rather than post-processing modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively fills high aspect ratio structures without voids, improving the reliability and performance of vertical semiconductor devices by using conductive layers with distinct wet etch rates to create a stable and protective barrier oxide.
Implementation Method 1
using conductive layers with distinct wet etch rates to create a stable and protective barrier oxide
Data Source
AI summary
A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.