Vertically Extended Source/Drain Structure to Prevent S/D Merging
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Solution Overview
Problem
The existing semiconductor technology faces challenges in reducing contact resistance in transistors, leading to increased transistor delay, and is susceptible to volume loss and electrical leakage due to merged source/drain structures during fabrication, especially with reduced transistor pitches.
Innovation Solution
A source/drain structure with reduced lateral extension and enhanced vertical extension is implemented, utilizing an epitaxial growth process with varying growth temperatures to minimize contact resistance and prevent merging, thereby maintaining channel stress and reducing fabrication losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If source/drain structures are formed with reduced transistor pitches, then transistor integration density is improved, but volume loss and electrical leakage occur due to merging of adjacent structures
Solution Approach 1:
The source/drain structure employs asymmetric dimensional design where the lateral extension is intentionally reduced while the vertical extension is enhanced. This asymmetric configuration allows adjacent transistors to be placed closer together (improving integration density) while the vertical prominence of each source/drain structure prevents merging and electrical leakage between adjacent devices.
Solution Approach 2:
The invention transitions from a conventional planar source/drain structure to a vertically extended three-dimensional structure. By increasing the vertical dimension (height) while reducing the lateral dimension (width), the structure achieves better isolation between adjacent transistors in the lateral plane, preventing merging and electrical leakage while maintaining high integration density.
2Ease of manufacture
If conventional epitaxial growth process is used, then source/drain structure formation is simplified, but volume loss occurs during fabrication
Solution Approach 1:
The invention modifies the epitaxial growth process parameters, specifically using varying growth temperatures during different stages of source/drain formation. This parameter change enables precise control over the source/drain structure dimensions, achieving the desired reduced lateral extension and enhanced vertical extension while minimizing volume loss during fabrication.
Solution Approach 2:
The invention performs preliminary dimensional control during the epitaxial growth stage itself, rather than relying on subsequent processing steps. By pre-establishing the reduced lateral extension and enhanced vertical extension characteristics during growth, the structure is protected from volume loss in later fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor speed and yield by reducing contact resistance and preventing electrical leakage, while maintaining sufficient channel stress and avoiding volume loss during the fabrication process.
Implementation Method 1
utilizing an epitaxial growth process with varying growth temperatures
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.