Vertical Split-Gate Memory Cell Layout for Higher Current Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to further scale down the size of non-volatile memory cells while maintaining performance, as shrinking channel width in planar structures reduces current flow and requires more sensitive sense amplifiers, and Fin-FET structures, although beneficial, do not fully address this challenge.
Innovation Solution
The development of vertically oriented non-volatile memory cells with gates that laterally wrap around a channel region, allowing for increased current flow without increasing semiconductor footprint, and enabling further scaling down of memory cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel width is shrunk in planar structures to scale down memory cell size, then the memory cell size is reduced, but the current flow is reduced
Solution Approach 1:
The patent transitions from a planar channel structure to a vertically extending channel structure. The channel region extends vertically from the semiconductor substrate surface, allowing current to flow in the vertical direction rather than horizontally. This dimensional change enables the channel length to be extended vertically while maintaining a small horizontal footprint, thereby preserving current flow characteristics while achieving scaled-down memory cell size.
Solution Approach 2:
The patent employs multiple gates (first gate, second gate, third gate, fourth gate) that laterally wrap around and are positioned at different vertical levels along the channel. These gates are nested vertically, with each gate controlling a specific vertical segment of the channel. This nested arrangement allows for precise control of current flow through the vertical channel while maintaining compact horizontal dimensions.
2Reliability
If Fin-FET structures are used to increase channel width, then current flow is increased, but the semiconductor footprint is increased
Solution Approach 1:
Instead of extending the channel horizontally as in Fin-FET structures, the patent extends the channel vertically from the semiconductor substrate surface. This vertical extension allows the channel length to be increased without increasing the horizontal footprint, achieving enhanced current flow control while maintaining compact device dimensions.
Solution Approach 2:
Multiple gates are positioned at different vertical levels, laterally wrapping around the vertical channel. This nested vertical arrangement of gates allows for extended channel control and increased current flow capability while keeping the horizontal footprint minimal, as all gates are stacked vertically rather than spread horizontally.
3Reliability
If vertically oriented memory cells are implemented, then current flow is enhanced and scaling is improved, but device complexity is increased
Solution Approach 1:
The vertical channel is divided into multiple segments, with each segment controlled by a separate gate (first gate, second gate, third gate, fourth gate) positioned at different vertical levels. This segmentation allows for independent control of different channel regions, enabling complex memory operations while maintaining a structured and manageable device architecture.
Solution Approach 2:
The vertically oriented channel structure with multiple laterally wrapping gates serves multiple functions: it provides enhanced current flow control, enables scaled-down memory cell size, and allows for selective control of different channel segments. This multi-functional design achieves several objectives simultaneously without requiring separate structures for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertically oriented memory cells enhance current flow and reduce the risk of program disturb, allowing for more memory cells in the same area with improved scaling and performance, and can be integrated with conventional transistors.
Implementation Method 1
A floating gate laterally wrapping around and insulated from a first portion of the channel region
Implementation Method 2
a channel region of the semiconductor member extends between the first region and the second region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having an upper surface with a semiconductor member extending vertically from the upper surface, wherein the semiconductor member has a first conductivity type. A first region of a second conductivity type different than the first conductivity type is formed at a proximal end of the semiconductor member adjacent the upper surface. A second region of the second conductivity type is formed at a distal end of the semiconductor member. A channel region of the semiconductor member extends between the first and second regions. A floating gate laterally wraps around a first portion of the channel region. A control gate laterally wraps around the floating gate. A select gate laterally wraps around a second portion of the channel region. An erase gate laterally wraps around the semiconductor member.