Vertical SRAM Cell With Silicide Interconnects
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Solution Overview
Problem
SRAM cells using Surrounding Gate Transistors (SGTs) face challenges in achieving a small surface area while maintaining stable operation, as minimizing wiring dimensions increases resistance, and enlarging them increases the cell surface area.
Innovation Solution
The SRAM cell design incorporates a silicide layer connecting N+ and P+ diffusion layers, eliminating the need for isolation layers between source and drain diffusion layers, and optimizing transistor placement to reduce surface area and improve operating margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power source potential wiring and ground potential wiring are formed with minimum dimensions, then SRAM cell surface area is reduced, but resistance increases making stable operation impossible
Solution Approach 1:
The patent transitions from planar wiring to vertical wiring by forming power source potential wiring and ground potential wiring that extend in the vertical direction through the semiconductor substrate. This dimensional change allows the wiring to achieve low resistance through increased cross-sectional area in the vertical dimension while maintaining a compact planar footprint, thereby resolving the contradiction between small cell area and stable operation.
Solution Approach 2:
The patent merges the power source potential wiring and ground potential wiring with the source and drain diffusion layers of the transistors. Specifically, the power source potential wiring is formed integrally with the source diffusion layer of PMOS transistors, and the ground potential wiring is formed integrally with the drain diffusion layer of NMOS transistors. This merging eliminates the need for separate wiring structures, reducing both resistance and cell area while ensuring stable operation.
2Reliability
If power source potential wiring and ground potential wiring are enlarged to attain stable operation, then resistance decreases, but SRAM cell surface area increases
Solution Approach 1:
The patent uses vertical wiring structures that extend through the semiconductor substrate, achieving low resistance through increased cross-sectional area in the vertical dimension rather than expanding the planar dimensions. This allows stable operation to be attained without increasing the SRAM cell surface area.
Solution Approach 2:
The patent combines the wiring functions with the transistor source and drain regions, so that the same structures serve dual purposes: as transistor terminals and as power/ground distribution pathways. This merging achieves low resistance for stable operation while minimizing the additional area required beyond the transistor structures themselves.
3Reliability
If isolation layers are formed between source and drain diffusion layers, then transistor performance is improved, but manufacturing complexity and cell area increase
Solution Approach 1:
The patent extracts and eliminates the isolation layer structure from between source and drain diffusion layers. Instead of forming isolation layers in these regions, the patent relies on the inherent properties of the diffusion layers and their integration with the vertical wiring structures to achieve the necessary electrical isolation and transistor performance, thereby reducing manufacturing complexity and cell area.
Solution Approach 2:
The patent enables the source and drain diffusion layers to serve their own isolation function through their spatial arrangement and integration with the vertical wiring structures. The diffusion layers themselves, combined with the vertical wiring configuration, provide the necessary electrical isolation without requiring additional isolation layer materials or processing steps.
Data Source
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Figure 3A
AI summary
In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain (4a), gate (18) and source (16) formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer (23a), the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer (13a) formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well (1a) positioned on the substrate are surrounded by a first anti-leak diffusion layer (1b) and a second anti-leak diffusion layer (1c) having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.