Vertical SRAM Cell Layout for Higher Memory Density
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Solution Overview
Problem
Existing SRAM cells face challenges in scaling down due to their horizontal device structure, which limits integration and storage density.
Innovation Solution
The development of a static random access memory (SRAM) cell with a vertical nanosheet/nanowire metal oxide semiconductor field effect transistor (MOSFET) structure, where transistors are stacked vertically to improve integration and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a horizontal device structure is used in SRAM cells, then the device can be manufactured with conventional processes, but the device cannot be scaled down further and integration is limited
Solution Approach 1:
The patent transitions from a planar horizontal device structure to a vertical three-dimensional structure. The source, gate, and drain are arranged vertically along the channel direction perpendicular to the substrate surface, enabling further scaling by utilizing the vertical dimension rather than being constrained to lateral scaling in the horizontal plane.
2Device complexity
If a horizontal device structure is used in SRAM cells, then the device layout is simple, but the integration and storage density cannot be increased
Solution Approach 1:
By stacking transistors vertically and arranging source-gate-drain structures in the vertical dimension, the patent increases the number of devices that can be integrated within the same horizontal footprint. This vertical stacking approach directly increases storage density without requiring more complex lateral interconnect routing.
3Length of moving object
If vertical devices are used in SRAM cells, then the device can be scaled down and integration improved, but the device structure becomes more complex
Solution Approach 1:
The vertical device structure segments the source, gate, and drain into distinct vertical regions along the channel. This segmentation allows each component to be optimized independently while maintaining a compact overall structure, facilitating scaling without proportionally increasing complexity.
Solution Approach 2:
The vertical arrangement allows nested positioning where the gate wraps around or is positioned adjacent to the channel, and source/drain regions are nested vertically. This nesting approach maximizes space utilization and reduces the horizontal footprint while maintaining functional separation of components.
Data Source
AI summary
A static random access memory (SRAM) cell includes: a substrate; first and second interconnection structures parallel to an upper surface of the substrate and opposite to each other; a first pull-down (PD) transistor and a first pass gate (PG) transistor on the first interconnection structure; a second PD transistor and a second PG transistor on the second interconnection structure; a first pull-up (PU) transistor under the first interconnection structure and overlapping vertically with the first PD transistor; and a second PU transistor under the second interconnection structure and overlapping vertically with the second PD transistor. Channel layers of the first PU, PD, PG transistors are offset from the first interconnection structure on a side away from the second interconnection structure. Channel layers of the second PU, PD, PG transistors are offset from the second interconnection structure on a side away from the first interconnection structure.