Vertical SRAM Metal Contacts on Sidewalls
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vertical SRAM cells face challenges in maintaining proper electrical continuity and preventing contamination of metal contacts and cross-coupled contacts with channels as they are downsized, due to increased leakage currents and difficulty in landing metal contacts on shrinking substrate areas.
Innovation Solution
The solution involves disposing metal contacts on the sidewalls rather than the top surfaces of the bottom source/drain regions, and ensuring cross-coupled contacts only land on metal contacts, thereby reducing the likelihood of contact and contamination with the channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical FinFETs are used to increase density, then the number of SRAM cells per substrate area increases, but metal contacts become increasingly difficult to place on bottom source/drain regions without contaminating channels
Solution Approach 1:
The patent transitions metal contacts from a horizontal placement configuration to a vertical sidewall placement configuration. Instead of placing metal contacts on the top surface of bottom source/drain regions (horizontal dimension), the contacts are formed on the vertical sidewalls of the bottom source/drain regions, utilizing the vertical dimension to achieve both high density and reliable electrical contact without channel contamination.
2Productivity
If SRAM cells are downsized to increase density, then more cells fit in the substrate plane, but the surface area of bottom source/drain regions for metal contact placement decreases
Solution Approach 1:
The invention moves metal contacts from the horizontal top surface of bottom source/drain regions to the vertical sidewalls. This dimensional transition provides additional contact area on the sidewalls that is not affected by horizontal downsizing, thereby maintaining adequate contact area even as cell size decreases.
3Area of stationary object
If metal contacts are placed closer to vertical channels to save space, then substrate area is reduced, but the risk of contact contamination and electrical shorts increases
Solution Approach 1:
The patent introduces an intermediary dielectric layer between the metal contacts and the vertical channels. This dielectric barrier prevents direct contact between the metal contacts and channels, eliminating the contamination risk while allowing the metal contacts to be positioned close to the channels for space efficiency.
4Ease of manufacture
If horizontal FinFETs are used in SRAM cells, then manufacturing is simpler, but leakage currents increase as channels become smaller
Solution Approach 1:
The patent transitions from horizontal FinFET configuration to vertical FinFET configuration. This vertical orientation provides better channel control and reduced leakage currents while maintaining manufacturability, as the vertical structure allows for effective gate control over the channel even at scaled dimensions.
Data Source
AI summary
A vertical SRAM cell includes a first (1st) inverter having a 1st pull-up (PU) transistor and a 1st pull-down (PD) transistor. The 1st PU and 1st PD transistors have a bottom source/drain (S/D) region disposed on a substrate and a channel extending upwards from a top surface of the bottom S/D region. A second (2nd) inverter has a 2nd PU transistor and a 2nd PD transistor. The 2nd PU and 2nd PD transistors have a bottom S/D region disposed on the substrate and a channel extending upwards from a top surface of the bottom S/D region. A 1st metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 1st PU and 1st PD transistors. A 2nd metal contact is disposed on sidewalls, and not on the top surface, of the bottom S/D regions of the 2nd PU and 2nd PD transistors.