Vertical VGAA SRAM Stacking With Oxide Channels for BEOL Scaling
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Solution Overview
Problem
Current silicon-based transistors are reaching performance and scalability limits, and alternative semiconductor materials like germanium and III-V materials are costly and face challenges in ultra-thin body performance scalability.
Innovation Solution
The use of vertical gate all around (VGAA) transistors with channels formed from semiconductive-behaving oxide materials, allowing for vertical stacking of SRAM cells and integration with Back-End-Of-Line processes, utilizing 2D materials for improved transport properties and compatibility with BEOL processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon-based transistors are continuously scaled down to improve integration density, then more components can be integrated into a given area, but performance and scalability limits are reached
Solution Approach 1:
The patent transitions from planar transistor architectures to vertical channel structures, moving the scaling direction from lateral (2D) to vertical (3D). This dimensional change allows continued improvement of integration density while avoiding the performance degradation associated with excessive lateral scaling of silicon-based devices.
Solution Approach 2:
The patent changes the material parameter from conventional silicon to semiconductive-behaving oxide materials, which offer different electrical characteristics and scalability properties. This material parameter change enables improved performance scalability while maintaining integration density benefits.
2Reliability
If alternative semiconductor materials like germanium and III-V materials are used to overcome silicon limits, then performance can be improved, but manufacturing cost increases
Solution Approach 1:
The patent employs semiconductive-behaving oxide materials that can be formed using existing BEOL processes, effectively replacing expensive alternative materials like germanium and III-V compounds. These oxide materials provide comparable performance benefits at lower manufacturing cost by utilizing standard industrial processes.
Solution Approach 2:
The patent develops a universal manufacturing approach using BEOL-compatible processes that can form vertical channel structures with semiconductive oxide materials. This universal method replaces multiple specialized manufacturing processes required for different alternative materials, reducing overall manufacturing complexity and cost.
3Area of stationary object
If vertical stacking of SRAM cells is implemented to improve area efficiency, then device footprint is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into multiple stacked SRAM cell layers, with each layer containing vertically oriented channels. This segmentation allows the device to achieve high area efficiency while managing complexity through modular layering, where each layer can be processed using similar BEOL-compatible techniques.
Solution Approach 2:
The patent stacks SRAM cells in the vertical dimension rather than expanding laterally, transforming the device architecture from a 2D planar layout to a 3D stacked configuration. This dimensional change achieves superior area efficiency while the use of standard vertical processing techniques keeps manufacturing complexity manageable.
4Reliability
If 2D materials are used for channel formation to improve transport properties, then electrostatic control is enhanced, but process compatibility challenges arise
Solution Approach 1:
The patent employs semiconductive-behaving oxide materials that can be formed in-situ using standard BEOL deposition and processing techniques. These materials self-organize into vertical channel structures with excellent electrostatic control, eliminating the need for separate 2D material transfer and integration processes that would compromise BEOL compatibility.
Solution Approach 2:
The patent modifies the material parameters by using oxide materials with semiconductive behavior that can be deposited as thin films using conventional BEOL processes. This parameter change maintains the electrostatic control benefits of 2D-like materials while achieving full process compatibility with existing manufacturing workflows.
Data Source
AI summary
A memory device includes a first n-type transistor and a second n-type transistor formed of a first channel extending along a vertical direction and wrapped by first, second, third, fourth, and fifth metal tracks; a third n-type transistor and a fourth n-type transistor formed of a second channel extending along the vertical direction and is wrapped by fourth, sixth, seventh, eighth, and ninth metal tracks; a first p-type transistor formed of a third channel extending along the vertical direction and is wrapped by second, third, and tenth metal tracks; and a second p-type transistor formed of a fourth channel extending along the vertical direction and is wrapped by sixth, seventh, and tenth metal tracks.