Vertical-Channel SRAM Stacking With Oxide VGAA Transistors
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Solution Overview
Problem
Current silicon-based transistors are reaching performance and scalability limits, and alternative semiconductor materials like germanium and III-V materials are costly and challenging to integrate effectively, especially in ultra-thin body configurations.
Innovation Solution
The development of semiconductor devices using vertically gate all around (VGAA) transistors with channels made of semiconductive-oxide materials, allowing for vertical stacking of SRAM cells and integration of 2D materials for enhanced performance and compactness, compatible with Back-End-Of-Line processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon-based transistors are used with repeated reductions in minimum feature size, then integration density improves, but performance and scalability reach limits
Solution Approach 1:
The patent transitions from planar 2D transistor channels to vertical 3D channels that extend through multiple metallization layers. This dimensional change allows continued scaling and performance improvement by utilizing the vertical dimension rather than relying solely on reducing lateral feature sizes, thereby overcoming the limits of silicon-based planar transistors
Solution Approach 2:
The patent employs semiconductive-oxide materials (such as IGZO - indium gallium zinc oxide) as channel materials instead of conventional silicon. These oxide semiconductor materials provide superior electrostatic control and carrier mobility, enabling transistors to overcome the performance and scalability limitations of silicon-based devices while maintaining compatibility with existing CMOS fabrication processes
2Reliability
If alternative semiconductor materials like germanium and III-V materials are used, then performance improves, but cost increases and integration becomes challenging
Solution Approach 1:
The patent changes the material parameter from conventional silicon or expensive III-V materials to oxide semiconductors (e.g., IGZO). These materials can be deposited using low-cost sputtering or atomic layer deposition (ALD) techniques at relatively low temperatures, achieving high performance while maintaining cost-effectiveness and compatibility with standard CMOS back-end-of-line processes
Solution Approach 2:
The patent applies oxide semiconductor materials specifically to the channel region of the transistor while maintaining conventional silicon-based structures for other components. This localized use of advanced materials provides performance benefits where needed without requiring complete replacement of the manufacturing ecosystem, thereby reducing integration complexity and cost
3Productivity
If vertical stacking of memory cells is implemented, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into multiple stacked memory cell layers, with each layer containing complete transistor functionality. The vertical channels extend through multiple metallization layers that are segmented into different functional blocks (word lines, bit lines, select lines), allowing independent fabrication and testing of each layer while achieving high integration density through stacking
Solution Approach 2:
The patent designs the vertical channel structure and metallization network to serve multiple functions simultaneously. The same vertical channel can be controlled by different gate electrodes at various heights, and the metallization layers are configured to provide multiple wiring functions (word lines, bit lines, select lines, power lines) throughout the vertical stack, reducing the need for additional specialized structures
Data Source
AI summary
A memory device includes a first n-type transistor and a second n-type transistor formed of a first channel extending along a vertical direction and wrapped by first, second, third, fourth, and fifth metal tracks; a third n-type transistor and a fourth n-type transistor formed of a second channel extending along the vertical direction and is wrapped by fourth, sixth, seventh, eighth, and ninth metal tracks; a first p-type transistor formed of a third channel extending along the vertical direction and is wrapped by second, third, and tenth metal tracks; and a second p-type transistor formed of a fourth channel extending along the vertical direction and is wrapped by sixth, seventh, and tenth metal tracks.