Vertical Semiconductor Stack Patterning With Stepped Alignment Keys
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving accurate overlay and preventing defects such as cracking and arcing during the formation of pillar structures, particularly due to limitations in alignment key design and etching processes.
Innovation Solution
The method involves forming a substrate with alternating stacks of dielectric and sacrificial layers, creating stepped alignment keys that serve as etching barriers to form precise patterns and pillar structures, and replacing sacrificial layers with gate electrodes, thereby enhancing alignment accuracy and preventing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment key design is used, then fabrication process is simple, but overlay accuracy deteriorates
Solution Approach 1:
The alignment key is divided into multiple segments including a first alignment key portion and a second alignment key portion with different etch selectivities. This segmentation allows each portion to serve specific functions: the first portion provides standard alignment reference while the second portion creates controlled etch barriers, thereby improving overlay accuracy without excessive complexity
Solution Approach 2:
The alignment key structure is extended into the vertical dimension by creating stepped configurations with different heights and etch depths. The first and second alignment key portions are positioned at different vertical levels, creating a three-dimensional structure that provides both alignment reference and etch barrier functions simultaneously
2Reliability
If etching process is performed without stepped alignment keys, then process steps are reduced, but defects such as cracking and arcing increase
Solution Approach 1:
The stepped alignment keys are formed in advance before the main etching process. The first alignment key portion is formed to a first depth and the second alignment key portion is formed to a second depth, creating pre-positioned etch barriers that prevent cracking and arcing during subsequent etching operations
Solution Approach 2:
The second alignment key portion acts as an intermediary etch barrier between the etching process and the underlying structures. By being positioned at a different depth than the first alignment key portion, it provides intermediate protection against etch-induced defects while allowing the etching process to proceed
3Measurement precision
If simple alignment key structure is used, then manufacturing is easier, but alignment key signal variation increases
Solution Approach 1:
Different portions of the alignment key are assigned different local properties: the first alignment key portion has one etch selectivity and depth while the second alignment key portion has different etch selectivity and depth. This local differentiation ensures that each portion contributes optimally to signal stability without requiring complex fabrication across the entire structure
Data Source
AI summary
A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.