Vertical Semiconductor Structure With Stack Contact for Dense Integration
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Solution Overview
Problem
Horizontal type semiconductor devices face challenges in reducing area occupation due to the parallel arrangement of source, gate, and drain, leading to poor performance such as increased power consumption and resistance, making it difficult to further miniaturize these devices.
Innovation Solution
A vertical type semiconductor device is developed with a substrate featuring a vertical active region, including source/drain regions and a channel region, surrounded by a gate stack, which allows for reduced area occupation and improved performance by eliminating the need for high-depth contact holes and reducing lithographic misalignment, thereby increasing integration density and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If horizontal type device arrangement is used, then source, gate, and drain can be arranged in parallel, but area occupation cannot be reduced further and device performance deteriorates
Solution Approach 1:
The patent transitions from a horizontal arrangement of source, gate, and drain to a vertical arrangement, utilizing the vertical dimension to achieve both area reduction and maintained performance. The gate electrode extends in the vertical direction above the channel layer, creating a three-dimensional structure that resolves the contradiction between miniaturization and performance.
2Area of stationary object
If area of horizontal type device is reduced, then area occupation decreases, but power consumption and resistance increase
Solution Approach 1:
By arranging the source, gate, and drain vertically rather than horizontally, the patent achieves area reduction without increasing power consumption. The vertical configuration maintains efficient current flow paths while minimizing the footprint, thereby resolving the contradiction between miniaturization and energy efficiency.
3Ease of manufacture
If high-depth contact holes are formed, then contact portions can be created, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent extracts the contact portion formation process from the complex high-depth contact hole etching process. By designing the device structure to eliminate the need for deep contact holes, the manufacturing process is simplified while still achieving the necessary electrical connections, thereby resolving the contradiction between manufacturability and process complexity.
4Manufacturing precision
If photolithography steps are increased, then alignment precision can be improved, but manufacturing cost and process time increase
Solution Approach 1:
The patent merges multiple photolithography steps into fewer steps by designing a device structure that requires less complex alignment. The vertical arrangement and simplified contact portion formation allow for reduced lithographic steps while maintaining alignment precision, thereby resolving the contradiction between manufacturing precision and productivity.
Data Source
AI summary
Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion. The lower layer portion contains at least the same element as the first source/drain region, the middle layer portion contains at least the same element as the channel region, and the upper layer portion contains at least the same element as the second source/drain region.