Vertical Stack Memory Device Void Gate Electrode Integration
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Solution Overview
Problem
Next-generation semiconductor memory devices face challenges in scaling memory cells due to packaging height limits, leading to reduced integration density and potential deterioration of resistance change characteristics in vertical NAND structures.
Innovation Solution
A memory device with a vertical stack structure featuring a protrusion portion, a recording material layer, and a gate electrode configuration that includes a void between the recording material layer and the insulating structure, which prevents direct contact and maintains stable resistance change characteristics, allowing for reduced physical separation distances between gate electrodes and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the physical separation distance between gate electrodes is reduced to increase integration density, then integration density is improved, but resistance change characteristics may deteriorate
Solution Approach 1:
The patent introduces a vertical protrusion portion extending from the insulating structure surface, creating a three-dimensional configuration. This allows the gate electrode to be positioned closer horizontally while maintaining adequate vertical separation through the protrusion height (L1 ≥ 5 nm), thus increasing integration density without compromising resistance change characteristics.
Solution Approach 2:
The recording material layer acts as an intermediary between the gate electrode and the insulating structure. By controlling its thickness (0.5 nm ≤ L2 ≤ 30 nm) and composition, it mediates the interaction between the gate electrode and substrate, enabling stable resistance change characteristics even at reduced separation distances.
2Reliability
If the protrusion length is increased to improve electrical separation, then resistance change characteristics are stabilized, but device height increases approaching packaging limits
Solution Approach 1:
The patent optimizes the protrusion length parameter (L1 ≥ 5 nm) to achieve the minimum effective electrical separation. This parameter change ensures stable resistance change characteristics while minimizing the vertical dimension to avoid approaching packaging height limits.
Solution Approach 2:
The protrusion portion creates localized electrical separation only where needed (between gate electrode and insulating structure), rather than increasing the overall device height uniformly. This local quality approach maintains electrical separation effectiveness while controlling total device dimensions.
Data Source
AI summary
Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.