Vertical Stack Nonvolatile Memory with Selective Voltage Control
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high integration and low power characteristics, particularly in enabling random access to memory cells, which is crucial for next-generation neuromorphic computing platforms.
Innovation Solution
The implementation of a nonvolatile memory device with a memory cell array featuring a vertical stack structure, where a control logic applies distinct non-selection voltages to different memory cells to adjust their Fermi levels, allowing for selective operation of memory cells and reducing power consumption through optimized voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a vertical stack structure to increase integration density, then the integration density is improved, but power consumption increases due to difficulty in selective access
Solution Approach 1:
The patent applies different voltage levels to different memory cells in the vertical stack based on their position and selection state. Specifically, the control logic applies a first non-selection voltage to a first memory cell, a second non-selection voltage to a second memory cell, and a selection voltage to a third memory cell, creating localized voltage conditions that enable selective access while maintaining high integration density
Solution Approach 2:
The patent changes the voltage parameter applied to different memory cells to achieve selective access. By adjusting the voltage levels (first non-selection voltage, second non-selection voltage, and selection voltage) and controlling the Fermi levels of semiconducting layers, the patent enables random access to specific memory cells in the vertical stack, thereby reducing power consumption while maintaining high integration density
2Adaptability or versatility
If random access to memory cells is enabled for neuromorphic computing, then computing capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the control of memory cells by dividing them into different groups (first memory cell, second memory cell, third memory cell) with different voltage control schemes. The control logic is segmented to handle different voltage levels independently, allowing random access capability while managing device complexity through modular control architecture
Solution Approach 2:
The control logic is designed with multi-functionality to handle multiple voltage levels (first non-selection voltage, second non-selection voltage, selection voltage) and perform multiple operations (write, erase, read) on different memory cells. This universal control approach enables random access for neuromorphic computing without proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell integration density and reduces power consumption by enabling efficient write, erase, and read operations, addressing the scaling issues in next-generation VNAND devices and supporting neuromorphic computing applications.
Implementation Method 1
applying a first non-selection voltage to the first memory cell, applying a second non-selection voltage different from the first non-selection voltage to the third memory cell... such that a semiconducting layer included in the first memory cell and a semiconducting layer included in the third memory cell have different Fermi levels
Data Source
AI summary
A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.