Vertical Stack Semiconductor Device for Uniform Drain Currents
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Solution Overview
Problem
Inverter fabrication faces challenges in achieving uniform drain currents for PMOS and NMOS transistors due to varying line widths and the high cost associated with altering silicon crystalline structures, leading to economical limitations.
Innovation Solution
A semiconductor device is fabricated using PMOS and NMOS transistors in a vertical stack structure with specific metal line contacts to unify drain currents, employing a silicon-on-insulator substrate and differentiated channel active regions to standardize line widths and reduce fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of the PMOS transistor is increased to match the drain current characteristics of PMOS and NMOS transistors, then the drain current uniformity is improved, but the manufacturing precision deteriorates due to different line widths between PMOS and NMOS transistors
Solution Approach 1:
The patent transitions from planar transistor configuration to vertical stack structure, stacking PMOS and NMOS transistors vertically. This dimensional change allows both transistor types to share the same line width while achieving equal drain currents through the vertical architecture, resolving the contradiction between drain current uniformity and manufacturing precision.
Solution Approach 2:
The patent changes the structural parameters by implementing a vertical stack configuration where PMOS and NMOS transistors are stacked vertically with shared line widths. This parameter change enables both transistor types to have identical line width dimensions while maintaining equal drain current characteristics through the vertical arrangement.
2Reliability
If the silicon crystalline structure is altered from 100 to 110 to become appropriate for drain current characteristics, then the drain current uniformity is improved, but the manufacturing cost increases
Solution Approach 1:
The patent changes the structural parameters by implementing a vertical stack configuration where PMOS and NMOS transistors are stacked vertically with shared line widths. This parameter change enables both transistor types to have identical line width dimensions while maintaining equal drain current characteristics through the vertical arrangement.
Data Source
AI summary
A semiconductor device includes a P-channel metal-oxide semiconductor (PMOS) transistor and an N-channel metal-oxide semiconductor (NMOS) transistor formed in three or more fin active regions in a vertical stack structure, an input metal line contacting gates of the PMOS transistor and NMOS transistor, a power supply voltage metal line contacting four channel active regions of the PMOS transistor, a contact metal line contacting two channel active regions of the NMOS transistor, and an output metal line contacting four channel active regions of the PMOS transistor and the NMOS transistor.