Vertically Stacked CMOS Structures for Higher Transistor Density
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Solution Overview
Problem
The challenge of increasing transistor density in semiconductor devices is becoming more difficult due to physical and material limitations from dimension shrink, limiting the effectiveness of traditional CMOS devices with side-by-side NMOS and PMOS transistors.
Innovation Solution
A stacked device structure is implemented by vertically stacking NMOS and PMOS transistors on separate substrates and bonding them to form CMOS devices, utilizing gate-all-around (GAA) and FinFET configurations with gate electrodes on multiple sides of the channel, and incorporating metal-insulator-metal memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dimension shrink is used to increase transistor density, then transistor density increases, but physical and material limitations prevent further shrinkage
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional stacked configurations, where multiple transistor layers are vertically stacked above each other. This vertical stacking enables continued transistor density improvement without further lateral dimension shrink, effectively resolving the physical limitations of traditional scaling approaches.
Solution Approach 2:
The patent implements nested transistor structures where transistors are stacked in multiple layers, with each layer containing complete transistor devices. The gate structures wrap around channel regions in a nested configuration, with gates positioned at different vertical levels surrounding the channel, creating a compact nested arrangement that maximizes density.
2Quantity of substance
If NMOS and PMOS transistors are placed side-by-side in the same horizontal plane, then CMOS device functionality is achieved, but transistor density is reduced
Solution Approach 1:
The patent separates NMOS and PMOS transistors into different vertical layers instead of placing them side-by-side in the same horizontal plane. This vertical separation allows both transistor types to coexist in a stacked configuration, achieving high-density CMOS functionality without the area constraints of planar layouts.
Solution Approach 2:
The patent divides the CMOS device into separate functional layers, with NMOS transistors in one layer and PMOS transistors in another layer. This segmentation allows independent optimization of each transistor type while maintaining compact vertical integration, resolving the conflict between CMOS functionality and density.
3Reliability
If gate coverage is extended to wrap around the channel, then resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate structure is configured to wrap around and surround the channel region in a nested arrangement, with gate material positioned at multiple vertical levels encircling the channel. This gate-all-around configuration maximizes gate control and reduces resistance by providing multiple conduction paths, while the nested structure enables systematic fabrication through sequential deposition and patterning steps.
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.