Vertical Stacked FET Logic Gate Density
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Solution Overview
Problem
The challenge is to increase the density of logic gates on semiconductor chips, as conventional CMOS logic arrangements of NFETs and PFETs are not optimized for efficient vertical stacking, leading to higher manufacturing costs and reduced functionality per chip size.
Innovation Solution
The solution involves vertically stacking N-channel Field Effect Transistors (NFETs) and P-channel Field Effect Transistors (PFETs) on a semiconductor substrate, with independently controllable gate electrodes connected to different logical signals, allowing for dense packing in NAND and NOR circuit configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional CMOS logic arrangements of NFETs and PFETs are used, then ease of manufacture is maintained, but logic gate density is insufficient
Solution Approach 1:
The patent transitions from conventional planar (2D) arrangement of transistors to a vertical (3D) stacked configuration. Multiple NFETs and PFETs are stacked vertically with their channels aligned in the same direction, enabling higher logic gate density by utilizing the third dimension (vertical space) rather than only horizontal plane arrangement.
Solution Approach 2:
The invention segments the transistor stack into distinct functional units where each transistor (NFET or PFET) is independently controllable with its own gate electrode. This segmentation allows individual transistors to be controlled by different logical signals, enabling complex logic gate functionality while maintaining a compact vertical structure.
2Quantity of substance
If vertically stacked FETs are implemented, then logic gate density increases, but manufacturing complexity increases
Solution Approach 1:
The patent achieves vertical stacking by extending the conventional planar transistor structure into the vertical dimension. The channel regions of multiple transistors are aligned vertically, and gate electrodes are positioned at different heights, allowing dense packing while using adapted conventional manufacturing techniques for semiconductor devices.
Solution Approach 2:
The vertical stack structure serves multiple functions: it provides mechanical support, electrical isolation between transistors, and a framework for independent gate control. The shared vertical channel alignment enables both NFETs and PFETs to be integrated in a unified structure that can implement various logic gates (NAND, NOR) without requiring completely new manufacturing processes.
3Quantity of substance
If more logic gates are placed on a chip, then functionality increases, but chip size remains constrained
Solution Approach 1:
By stacking transistors vertically, the patent effectively increases the functional capacity within the same chip footprint. The vertical arrangement allows multiple logic gates to be implemented in a compact volume, significantly increasing the number of transistors and logic gates that can be integrated on a single chip without proportionally increasing the chip's horizontal area.
Solution Approach 2:
The vertical stack structure nests multiple transistors within a compact vertical space, similar to nested dolls. Each transistor is positioned at a different height level within the stack, allowing maximum utilization of the vertical dimension. This nesting approach enables high-density integration where transistors are tightly packed in the vertical direction, maximizing functionality within constrained chip area.
Data Source
AI summary
Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.