Vertical Stacked Memory Module Reducing Signal Skew
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Solution Overview
Problem
Conventional microelectronic packages face challenges in achieving compactness and efficient signal transmission between multiple chips, leading to increased size and potential performance issues due to varying signal propagation delays and skew in multi-chip packages.
Innovation Solution
A microelectronic package design featuring a substrate with multiple pairs of microelectronic elements, where each pair has a lower microelectronic element with contacts arranged in specific axes and an upper element overlapping the lower one, along with electrical connections and terminals configured to minimize signal skew and reduce package size, allowing for efficient signal transmission and compact arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are packaged in a multi-chip package, then memory capacity and functionality are improved, but signal propagation delay and skew increase
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking, utilizing the third dimension (height) to accommodate multiple memory chips. This dimensional change reduces signal path length by allowing direct vertical connections through substrates, thereby decreasing propagation delay while maintaining high memory capacity.
Solution Approach 2:
The patent introduces intermediate substrates and redistribution layers as mediators between memory chips. These intermediaries provide optimized signal routing paths and impedance matching, reducing signal skew and propagation delay while enabling high-density chip interconnections.
2Area of moving object
If chip size is reduced to achieve compactness, then device size is reduced, but signal transmission performance deteriorates
Solution Approach 1:
The patent employs vertical stacking to reduce the horizontal footprint while maintaining signal transmission quality through controlled impedance vertical interconnects. This allows compact device size without compromising signal integrity.
Solution Approach 2:
The patent optimizes signal transmission parameters including impedance control, signal voltage levels, and timing margins to maintain reliable signal transmission in the compact vertical architecture, preventing performance deterioration despite reduced device size.
3Ease of manufacture
If conventional packaging is used, then manufacturing is simple, but package area is large
Solution Approach 1:
The patent implements vertical stacking with multiple memory chips arranged in layers above a single substrate, dramatically reducing the package footprint. This three-dimensional arrangement maintains manufacturing feasibility through established chip stacking and bonding processes.
Solution Approach 2:
The patent designs a universal substrate architecture that can accommodate different numbers and types of memory chips in various configurations, enabling flexible packaging solutions that reduce area while maintaining ease of manufacture through standardized interfaces and processes.
Data Source
AI summary
A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.