Vertical Stacked Power MOSFET Package Design
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Solution Overview
Problem
The existing approach to packaging multiple power MOSFET chips in semiconductor devices results in increased mounting area and parasitic inductance on the mounting board, leading to degraded power supply efficiency and larger electronic device sizes.
Innovation Solution
A semiconductor device design where a second power MOSFET chip is placed above a first chip, with specific alignment to avoid overlapping with the first chip's gate electrode, and both chips are sealed with resin, allowing for vertical stacking and reduced wiring parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple power MOSFET chips are individually packaged, then each chip is protected and functional, but the number of semiconductor packages increases, leading to increased mounting area and parasitic inductance
Solution Approach 1:
The patent combines multiple power MOSFET chips (first chip with high-side MOSFET, second chip with low-side MOSFET) into a single semiconductor package. The chips are mounted on a common substrate with integrated wiring, eliminating the need for separate packages and reducing mounting area while maintaining individual chip protection through the unified package structure.
Solution Approach 2:
The patent nests multiple chips within a single package structure. The first and second chips are mounted on the substrate and enclosed together with the wiring pattern within one semiconductor package, creating a nested arrangement where multiple functional units are contained within a single protective housing.
2Area of stationary object
If multiple power MOSFET chips are packaged together in one semiconductor package, then mounting area is reduced, but wiring parasitic inductance increases due to longer wiring paths
Solution Approach 1:
The patent implements local quality by creating short, localized wiring paths between the chips and package terminals. The wiring pattern is specifically designed to minimize the distance current must travel, with wiring regions positioned adjacent to each chip. This localizes the electrical connections and reduces parasitic inductance despite the integrated package structure.
Solution Approach 2:
The patent utilizes three-dimensional packaging arrangement where chips are mounted on different layers or positions of the substrate. The wiring connects chips and terminals in a compact 3D configuration rather than spreading out in two dimensions, reducing the overall wiring path length and parasitic inductance while maintaining reduced mounting area.
3Area of stationary object
If the second chip is placed directly above the first chip to minimize area, then mounting area is minimized, but the second chip overlaps with the first chip's gate electrode, causing electrical interference
Solution Approach 1:
The patent employs asymmetric positioning of the second chip relative to the first chip. Instead of direct vertical alignment that would cause overlap with the gate electrode, the second chip is positioned offset in a specific direction. This asymmetric arrangement minimizes mounting area while avoiding electrical interference by ensuring proper spatial separation of sensitive gate regions.
Solution Approach 2:
The patent performs preliminary positioning planning during the package design stage to determine the optimal location of the second chip. The layout is pre-configured to avoid overlap with the first chip's gate electrode, ensuring that electrical interference is prevented before the actual chip placement and packaging process occurs.
Data Source
AI summary
A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.