Vertical Stacked Semiconductor Unit Cells for High Integration Density
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing the size of unit cells to increase integration density, as design rule reductions are nearing limits and require high development costs, limiting the competitiveness and efficiency of semiconductor memory devices.
Innovation Solution
A method for manufacturing a semiconductor device with a multi-layered structure by vertically stacking unit cells, each comprising a transistor and a capacitor, on a semiconductor substrate, where the unit cells share a bit line and are configured in a double-layered structure to occupy a smaller 4F2-sized area, allowing for increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If design rule reduction is used to decrease unit cell size, then integration density is improved, but development cost increases significantly
Solution Approach 1:
The patent transitions from planar (2D) unit cell arrangement to vertical (3D) stacking of unit cells. By stacking multiple unit cells vertically on top of each other, the integration density is doubled without requiring further reduction of the minimum feature size F. This dimensional change allows achieving 2F2-sized unit cell area equivalent while maintaining the same fabrication process capabilities, thereby avoiding high development costs associated with design rule reduction.
2Quantity of substance
If unit cell size is reduced to increase integration density, then the number of chips per wafer increases, but manufacturing complexity increases
Solution Approach 1:
The invention introduces vertical stacking of unit cells as a new dimension, transforming the traditional planar arrangement into a three-dimensional structure. This approach increases integration density without proportionally increasing manufacturing complexity because the vertical stacking can be achieved through standard semiconductor fabrication processes such as sequential deposition and patterning, rather than requiring entirely new manufacturing techniques.
Solution Approach 2:
The unit cell is segmented into multiple functional layers (capacitor layer, transistor layer, interconnect layers) that can be manufactured separately and then integrated vertically. This segmentation allows each layer to be optimized and manufactured using established processes, reducing overall manufacturing complexity while achieving high integration density through vertical integration.
3Ease of manufacture
If conventional planar unit cell structure is used, then manufacturing process is simple, but integration density is limited
Solution Approach 1:
The patent maintains manufacturing process simplicity by using standard semiconductor fabrication techniques while introducing vertical stacking to double the integration density. The multi-layered structure is built using sequential deposition, patterning, and etching processes that are already established in the industry, thus achieving higher density without sacrificing ease of manufacture.
Data Source
AI summary
A semiconductor device includes a substrate and a plurality of unit cells vertically arranged on the substrate.