Vertical Stacked SiP for Reduced RF Module Footprint
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Solution Overview
Problem
Traditional multi-chip modules (MCMs) face challenges in miniaturization due to the large size of system-on-a-chip (SoC), crystal, and crystal trace routing, which increases parasitic capacitance and affects the crystal's ability to oscillate at power up, making it difficult to design smaller wireless devices with greater functionality.
Innovation Solution
The implementation of a system-in-a-package (SiP) using vertical integration technologies, where the SoC, crystal, and other components are stacked on a substrate, reducing the package size, decreasing parasitic capacitance, and minimizing coupling between crystal routing traces and other sensitive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional MCM horizontal layout is used, then all components can be interconnected, but the package footprint becomes large
Solution Approach 1:
The patent transitions from horizontal layout to vertical stacking, arranging components (SoC, crystal, FEM, passive components) in multiple layers along the vertical dimension. This allows all components to be interconnected while dramatically reducing the package footprint, as components are stacked above and below each other rather than spread out horizontally.
Solution Approach 2:
The patent divides the MCM into multiple discrete layers or stacks, with each layer containing specific components (e.g., SoC layer, crystal layer, FEM layer, passive component layer). This segmentation enables vertical integration while maintaining interconnectivity through controlled impedance traces and vias between layers.
2Object-affected harmful factors
If long crystal routing paths are used in MCM, then all components can be connected, but parasitic capacitance increases
Solution Approach 1:
The patent routes crystal signals vertically through short traces on the same layer or adjacent layers, rather than horizontally across the package. This vertical routing approach dramatically reduces trace length and associated parasitic capacitance, while the increased routing complexity is managed through standardized via structures and controlled impedance designs.
Solution Approach 2:
The patent introduces intermediate structures such as via holes, through-silicon vias (TSVs), and intermediate connection layers to facilitate short vertical routing paths. These intermediaries enable direct vertical connections between crystal and SoC across multiple layers, minimizing horizontal trace length and parasitic capacitance.
3Area of stationary object
If vertical integration is implemented, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the vertical integration process into discrete manufacturing stages: substrate preparation, component placement on individual layers, vertical interconnection formation (vias/TSVs), and encapsulation. This segmentation enables complex vertical structures to be manufactured through standardized, repeatable processes rather than requiring entirely new manufacturing capabilities.
Solution Approach 2:
The patent employs universal manufacturing techniques and standardized components that can be adapted to vertical integration. Common processes such as reflow soldering, via formation, and encapsulation are used in the vertical architecture, allowing existing manufacturing infrastructure to be leveraged rather than requiring completely new specialized processes.
Data Source
AI summary
Methods to form stacked circuit assemblies include mounting a first wireless device component to a first surface of a substrate and placing a second wireless device component over the first wireless device component such that the first wireless device component is disposed between the second wireless device component and the first surface of the substrate such that a first overhanging portion of the second wireless device component extends beyond a periphery of the first wireless device component. The first wireless device component is in communication with the second wireless device component and second wireless device component is in communication with the substrate.