Vertical Stacked TFT Capacitor for High-Resolution OLED
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Solution Overview
Problem
As pixel sizes in organic light emitting display devices decrease to achieve higher resolution, the reduced size of thin film transistors and capacitors leads to degradation in device characteristics, including increased leakage currents and unstable drive current supply, resulting in poor display quality.
Innovation Solution
A thin film transistor array substrate design featuring a capacitor implemented by overlapping capacitor electrodes on the same layer as the gate electrodes of the transistors, with a capacitor hole penetrating the gate insulation film to increase capacitance, and using oxide semiconductor material for the second thin film transistor to minimize leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel area is decreased to achieve higher resolution, then the resolution is improved, but the area allocated for thin film transistors and capacitors is reduced, resulting in degradation of device characteristics
Solution Approach 1:
The patent applies three-dimensional stacking to arrange thin film transistors and capacitors in vertical layers rather than spreading them horizontally. Multiple capacitor electrodes and transistor components are positioned at different heights (first height, second height, third height), effectively utilizing the vertical dimension to maintain component area and performance while reducing pixel footprint for higher resolution displays.
2Measurement precision
If the area of the sampling thin film transistor is decreased, then the pixel density is improved, but the leakage current increases beyond the threshold
Solution Approach 1:
The sampling thin film transistor is configured in a vertical stacking arrangement where the active layer, gate electrode, and source/drain electrodes are positioned at different heights. This three-dimensional structure maintains sufficient effective area for low leakage current while reducing the horizontal footprint to increase pixel density.
3Measurement precision
If the area of the capacitor is decreased, then the pixel size is reduced, but the capacitance decreases, resulting in unstable drive current supply
Solution Approach 1:
The capacitor is constructed with multiple electrodes positioned vertically at different heights (first capacitor electrode at first height, second capacitor electrode at second height). This stacking configuration increases the effective capacitance by utilizing vertical separation distance while minimizing the horizontal area occupied, thereby maintaining stable drive current supply in smaller pixels.
Solution Approach 2:
The patent employs a composite insulating film structure consisting of a first gate insulation film, a second gate insulation film, and an intermediate insulation film between the capacitor electrodes. This multi-layer insulating composite provides optimized dielectric properties to enhance capacitance within the constrained vertical space of the stacked configuration.
4Measurement precision
If the size of thin film transistors and capacitors is reduced, then the resolution is improved, but the drive current becomes unstable
Solution Approach 1:
The vertical stacking arrangement of transistors and capacitors in three dimensions maintains sufficient component sizes for stable electrical characteristics while reducing the horizontal pixel footprint. This enables high resolution displays to achieve stable drive current supply through optimized vertical component placement rather than horizontal scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the capacitance of the capacitor and reduces leakage currents, maintaining display quality even with smaller pixel sizes, enabling the production of high-resolution organic light emitting display devices.
Implementation Method 1
a capacitor which is charged by the data signal
Implementation Method 2
an active layer of the second thin film transistor disposed on a second gate insulation film covering the first capacitor electrode
Data Source
AI summary
An embodiment of the present invention provides a thin film transistor array substrate having a first thin film transistor, a second thin film transistor and a capacitor connected with a gate electrode of the first thin film transistor, and a third thin film transistor connected with the capacitor, wherein the thin film transistor array substrate comprises a first capacitor electrode disposed on a first gate insulation film covering an active layer of the third thin film transistor; an active layer of the second thin film transistor disposed on a second gate insulation film covering the first capacitor electrode; a gate electrode of the second thin film transistor disposed on an intermediate insulation film covering a portion of active layer of the second thin film transistor; and a second capacitor electrode of the capacitor disposed on the intermediate insulation film and overlapped with the first capacitor electrode.