Vertically Stacked Static Memory Cell Architecture
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Solution Overview
Problem
There is a need for improved architectures for static memory cells that can be integrated into highly dense configurations, as existing static memory cells are limited by their larger transistor count and architectural differences compared to dynamic memory cells, making them less suitable for highly integrated applications.
Innovation Solution
The proposed solution involves vertically arranging static memory cells with paired inverters, utilizing nanowire-type transistors and dielectric material, and incorporating them into memory arrays with vertically stacked and laterally offset transistors to enable dense integration while maintaining stable operating states without the need for refreshing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static memory cells are designed with traditional architectural arrangements, then stable operating states are maintained, but packaging density is reduced due to larger transistor count
Solution Approach 1:
The patent transitions from planar arrangement to vertical stacking of transistors, moving the memory cell structure into the third dimension. This vertical integration allows multiple transistors to be stacked above each other, significantly reducing the lateral area occupied by each memory cell while preserving the bistable operation through maintained feedback paths between cross-coupled inverters
Solution Approach 2:
The patent combines multiple transistor functions into a vertically stacked configuration where transistors share common substrates and interconnect structures. This merging approach reduces the overall footprint by eliminating redundant lateral connections and allowing shared support infrastructure, thereby increasing packaging density without compromising circuit functionality
2Reliability
If static memory cells use more transistors compared to dynamic memory cells, then stable operating states are achieved, but device complexity increases
Solution Approach 1:
By stacking transistors vertically, the patent reduces the lateral spread required for each transistor and its connections. This dimensional transition allows the same number of transistors to occupy less area, or alternatively, enables more transistors to be integrated in the same footprint without proportionally increasing complexity of lateral interconnections
3Area of stationary object
If dynamic memory cells are used to achieve greater packaging density, then area is reduced, but reliability deteriorates due to lack of stable operating states requiring periodic refreshing
Solution Approach 1:
The vertical stacking architecture enables static memory cells to achieve higher density comparable to dynamic memory cells while preserving the cross-coupled inverter feedback mechanism. This maintains the bistable operation that eliminates the need for periodic refreshing, thus achieving both high density and reliability without requiring refresh circuits
Data Source
AI summary
Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated into first and second inverters having first and second inverter outputs, respectively. A first access transistor gatedly couples the first inverter output to a first comparative bitline, and second access transistor gatedly couples the second inverter output to a second comparative bitline. The first and second access transistors have first and second gates coupled to one another through a wordline. The four transistors are along a first side of the wordline, and are vertically displaced from the wordline. The first and second comparative bitlines are laterally adjacent to one another along a second side of the wordline, and are vertically displaced from the wordline. Some embodiments include memory arrays.