Vertical Semiconductor Structure Etch Stop Oxygen Doping
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Solution Overview
Problem
The complex and expensive processes involved in manufacturing vertical semiconductor devices, such as vertical gate-all-around transistors and FinFETs, necessitate a more efficient and cost-effective method for forming these devices.
Innovation Solution
A method utilizing cluster oxygen doping treatment and oxygen plasma doping to trim critical dimensions and reduce thermal annealing temperatures, improving the properties of isolation layers and eliminating the need for furnace annealing, which can damage SiGe/Ge/III-V semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing processes are used for vertical semiconductor devices, then the devices can be formed, but the processes are complex and expensive
Solution Approach 1:
The patent changes the thermal processing parameters by replacing high-temperature furnace annealing with lower-temperature rapid thermal processing. This parameter change simplifies the manufacturing process by eliminating the need for complex furnace annealing equipment and multi-step thermal cycles, while still achieving the desired device formation and properties
Solution Approach 2:
The patent extracts and eliminates the furnace annealing step from the conventional manufacturing process. By removing this complex and time-consuming thermal processing step, the overall process complexity is reduced while the essential device formation functions are maintained through alternative lower-temperature processing methods
2Ease of manufacture
If furnace annealing is used to treat isolation layers, then the layers can be processed, but SiGe/Ge/III-V semiconductor devices are damaged
Solution Approach 1:
The patent changes the temperature parameter from high-temperature furnace annealing to lower-temperature rapid thermal processing. This parameter change allows isolation layer processing to be performed without exposing temperature-sensitive SiGe/Ge/III-V semiconductor devices to damaging thermal conditions, thereby eliminating thermal damage while maintaining processing effectiveness
Solution Approach 2:
The patent skips the prolonged high-temperature furnace annealing step by implementing rapid thermal processing that achieves the same isolation layer treatment in a much shorter time at lower temperatures. This rushing through the thermal processing step prevents thermal damage accumulation in sensitive semiconductor materials
3Productivity
If critical dimensions are reduced to improve device scaling, then device density increases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent changes the thermal processing parameters to lower temperatures and shorter durations, which reduces thermal diffusion and minimizes variations in critical dimensions. This parameter change enables better manufacturing precision even as device scaling progresses, allowing higher device density to be achieved without sacrificing dimensional control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the robustness of vertical structures by maintaining thicker critical dimensions, reducing leakage current, and increasing breakdown voltage, while avoiding damage from thermal annealing and improving the manufacturing efficiency of semiconductor devices.
Implementation Method 1
A method utilizing cluster oxygen doping treatment and oxygen plasma doping to trim critical dimensions
Implementation Method 2
cluster oxygen doping treatment to trim critical dimensions and reduce thermal annealing temperatures, improving the properties of isolation layers
Data Source
AI summary
According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment.