Vertical Sidewall STT-MRAM for High Density Storage
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Solution Overview
Problem
Existing STT-MRAM structures face challenges in achieving high density memory with compact designs while maintaining low power consumption and avoiding complex three-dimensional layouts, which are necessary for scalable and reliable memory solutions.
Innovation Solution
The fabrication of vertical sidewall STT-MRAM structures involves forming a bottom electrode within an interlayer dielectric layer, followed by the deposition and patterning of anti-ferromagnetic, fixed, tunnel, and free layers, and top electrodes, allowing for a two-bit per cell architecture without the need for three-dimensional layouts or excessive power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MRAM structures are used to achieve high density memory, then memory density is improved, but device complexity and fabrication complexity increase due to required three-dimensional layouts
Solution Approach 1:
The patent transitions from planar two-dimensional MRAM cell layouts to a vertical three-dimensional structure where magnetic layers are stacked perpendicular to the substrate. This dimensional change allows achieving higher memory density without proportionally increasing layout complexity, as the vertical stacking efficiently utilizes the third dimension (height) rather than expanding horizontally.
Solution Approach 2:
The magnetic memory structure is segmented into multiple functional layers (pinned layer, free layer, tunnel barrier, electrode layers) stacked vertically. Each layer performs a specific function, and this segmentation allows independent optimization of each component while achieving high overall density through compact vertical integration.
2Reliability
If programming current is increased to switch magnetic states reliably, then write reliability is improved, but power consumption increases
Solution Approach 1:
The patent optimizes the magnetic anisotropy energy barrier and tunnel barrier thickness to reduce the critical switching current density. By carefully controlling material composition and layer thicknesses, the structure achieves reliable switching at lower current levels, reducing power consumption while maintaining write reliability.
Solution Approach 2:
The patent employs composite magnetic tunnel junction structures with specific material combinations (e.g., CoFeB, CoFe, MgO, Ta) that provide both high spin polarization for efficient switching and appropriate magnetic anisotropy for stable state retention. These composite materials enable reliable switching at reduced current densities compared to conventional single-material structures.
3Quantity of substance
If cell size is decreased to increase memory density, then memory density is improved, but write disturbance and half-select problem worsen
Solution Approach 1:
The patent implements local magnetic field confinement through precisely engineered magnetic layer configurations and shielding structures. The magnetic fields generated during writing are localized to the target cell region through controlled magnetization patterns in adjacent shield layers, preventing field leakage that would cause write disturbances in neighboring cells even as cell dimensions shrink.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of robust and reliable STT-MRAM structures with higher density memory while reducing power usage and simplifying the fabrication process, addressing the limitations of previous STT-MRAM technologies.
Implementation Method 1
The pinned layer polarizes the electron spin of the programming current, and torque is created as the spin-polarized current passes through the stack. The spin-polarized electron current interacts with the free layer by exerting a torque on the free layer. When the torque of the spin-polarized electron current passing through the stack is greater than the critical switching current density (JO), the torque exerted by the spin-polarized electron current is sufficient to switch the magnetization of the free layer.
Implementation Method 2
Magnetic Random Access Memory (MRAM) is a non-volatile computer memory technology based on magnetoresistance. The magnetic field of the programming current can cause the magnetic orientations of the two magnetic layers to be either parallel, giving a lower electrical resistance across the layers ('0' state), or antiparallel, giving a higher electrical resistance across the layers ('1' state).
Data Source
AI summary
A method of fabricating a vertical two-bits per cell STT MRAM for high density storage includes forming a bottom electrode within an interlayer dielectric (ILD) layer, forming an anti-ferromagnetic (AF) layer over the bottom electrode, and forming a fixed layer along sidewalls of the AF layer. The method further includes forming a tunnel layer along the fixed layer, forming a free layer along the tunnel layer, and forming a top electrode along the free layer and over an upper surface of the AF layer.