Vertical Surround-Gate Channel Structure for Higher ON/OFF Control
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Solution Overview
Problem
Existing planar semiconductor devices face challenges in scaling down due to their parallel arrangement of source, gate, and drain, which limits their performance in terms of ON current and OFF current.
Innovation Solution
A vertical semiconductor device is designed with a substrate, stacked source/drain layers, and a channel layer made of semiconductor materials like Ge, SiGe, or III-V compounds, which enhance ON current and reduce OFF current. A gate stack surrounds the channel layer to control the current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar device structure with parallel source, gate and drain arrangement is used, then manufacturing process is simple, but device scaling is limited and ON current is reduced
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement to a vertical three-dimensional structure. The source, gate and drain are stacked perpendicular to the substrate surface, with the channel layer extending vertically between source and drain regions. This dimensional change enables continued device scaling while maintaining effective gate control and improving ON current through enhanced carrier transport in the vertical channel.
2Productivity
If traditional Si-based channel material is used, then manufacturing process is mature, but ON current is limited and OFF current is high
Solution Approach 1:
The patent changes the material parameter of the channel layer from traditional silicon to advanced semiconductor materials such as Ge, SiGe, or III-V compounds. These materials possess superior electrical properties including higher carrier mobility and better bandgap characteristics, which directly increase ON current and reduce OFF current. The manufacturing process has been adapted to accommodate these materials through modified epitaxial growth techniques.
Solution Approach 2:
The patent employs composite material structures in the channel layer, such as SiGe alloys or III-V compound semiconductors, which combine the advantages of different materials. These composite materials provide both the mechanical compatibility needed for integration and the enhanced electrical properties required for superior current characteristics, balancing performance improvement with manufacturing feasibility.
3Productivity
If vertical device structure is adopted, then device scaling is improved and ON current is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by using epitaxial growth to form precisely controlled vertical layers before any patterning or gating steps. The channel layer, source regions and drain regions are sequentially deposited with atomic-layer precision, establishing the vertical structure's geometric accuracy early in the process. This preliminary formation of the stacked structure simplifies subsequent manufacturing steps while maintaining high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical semiconductor device achieves increased ON current and reduced OFF current compared to traditional Si-based devices, enabling improved device performance and scalability.
Implementation Method 1
the channel layer comprises a semiconductor material causing an increased ON current and/or a reduced OFF current as compared with Si
Implementation Method 2
a gate stack surrounding a periphery of the channel layer
Implementation Method 3
epitaxially growing a first source/drain layer on a substrate; epitaxially growing a channel layer on the first source/drain layer
Data Source
AI summary
A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.