Vertical Switch 3D Memory Array Leakage Control
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Solution Overview
Problem
Existing memory devices face challenges with high power consumption due to leakage currents in diode arrays, which increase geometrically with array size, and the use of current-level switching devices (CLSDs) adds complexity and expense due to their analog characteristics.
Innovation Solution
The development of memory arrays with vertically oriented MOS transistors that are tightly packed, utilizing conductive strapping features to compensate for series resistance and requiring lower supply voltages, while maintaining high packing density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If diode arrays are used to achieve high packing density, then area efficiency is improved, but power consumption increases due to geometrically growing leakage currents
Solution Approach 1:
The patent transitions from planar diode arrays to three-dimensional vertical transistor structures. By stacking source, channel, and drain layers vertically and extending bit lines and word lines into the third dimension, the invention achieves high packing density while reducing leakage through the inherent switching control of transistors compared to diodes.
Solution Approach 2:
The invention changes the fundamental operating parameters by using vertical transistor structures with controllable channel conductivity. The channel layer's electrical properties can be dynamically adjusted through gate control, enabling precise leakage current management while maintaining high density through vertical stacking of functional layers.
2Loss of energy
If current-level switching devices (CLSDs) are used to reduce leakage, then power consumption is improved, but device complexity increases due to analog characteristics
Solution Approach 1:
The patent replaces the analog current-level switching mechanism with digital transistor-based switching. The vertical MOSFET structures provide binary on/off control through gate voltage thresholds, eliminating the analog characteristics of CLSDs while maintaining low leakage through proper transistor sizing and threshold voltage control.
Solution Approach 2:
The invention changes the switching mechanism from current-level detection to voltage-threshold-based transistor switching. By controlling the gate-to-source voltage relative to the threshold voltage, the transistors provide clean digital switching behavior with minimal leakage in the off state, avoiding the analog complexity of CLSDs.
3Area of stationary object
If vertical MOS transistors are tightly packed to increase density, then area efficiency is improved, but series resistance increases requiring higher supply voltages
Solution Approach 1:
The patent extends conductive paths into the third dimension by stacking bit lines and word lines vertically. This three-dimensional routing allows shorter lateral connection lengths, reducing series resistance despite tight packing, and enables high density without proportionally increasing supply voltage requirements.
Solution Approach 2:
The invention implements nested vertical structures where source, channel, and drain layers are stacked within each other, and multiple bit lines and word lines are vertically integrated. This nesting reduces the lateral footprint and connection lengths, minimizing series resistance while maintaining high packing density.
Data Source
AI summary
Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F2. The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.