Vertical Sync Image Pipeline to Prevent High-Frame-Rate Loss

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Solution Overview

Problem

High frame rates in electronic devices lead to a higher possibility of frame loss, disrupting the continuity of display content and affecting user experience.

Innovation Solution

Implementing an image processing method that utilizes a second vertical synchronization signal (VSYNC_Render) to decouple the drawing and rendering processes, allowing for asynchronous completion within synchronization periods, and adjusting the signal timing to accommodate processing times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the frame rate is increased to improve visual smoothness, then the display quality is improved, but the possibility of frame loss increases

Engineering Contradiction:

Improveframe rateVSAvoidframe loss possibility

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent divides the frame processing into two independent stages: drawing stage (triggered by VSYNC_APP) and rendering stage (triggered by VSYNC_Render). This segmentation allows each stage to complete independently within its own time window, preventing frame loss even at high frame rates where a single-stage approach would fail.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The drawing operation is performed in advance before the rendering operation. The VSYNC_APP signal triggers drawing of the current frame while the VSYNC_Render signal triggers rendering, allowing the system to prepare frame data ahead of time and reduce the risk of frame loss during high-speed display operations.

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If drawing and rendering are performed in a single pipeline stage, then the process is simple, but frame loss occurs at high frame rates

Engineering Contradiction:

Improvepipeline structureVSAvoidframe loss possibility

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent segments the single drawing-rendering pipeline into two separate pipeline stages, each with its own vertical synchronization signal. This increases structural complexity but eliminates frame loss by providing independent time windows for each operation, making the system more reliable at high frame rates.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary buffer between the drawing and rendering stages. This buffer allows the drawing thread to complete its work and pass data to the rendering thread without requiring immediate processing, decoupling the two operations and preventing frame loss.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Device complexity

If drawing and rendering are performed sequentially in one synchronization period, then the timing is simple, but the processing may not complete before the next frame

Engineering Contradiction:

Improvesynchronization timingVSAvoidframe completion timing

Core Design Contradiction:

Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the single synchronization period into two separate synchronization periods: one for drawing (VSYNC_APP) and one for rendering (VSYNC_Render). This allows each operation to have its own dedicated time window, ensuring that both drawing and rendering can complete without overlapping or missing frame deadlines.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent makes the synchronization timing dynamic by allowing drawing and rendering to occur at different intervals. The system can adjust the timing of VSYNC_APP and VSYNC_Render signals independently based on processing requirements, optimizing frame completion timing while maintaining simplicity in the synchronization mechanism.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12548536B2Image processing method based on vertical sychronization signal and electronic device

Publication Date: 2026.02.10 HUAWEI TECH CO LTD

AI summary

An image processing method based on a vertical synchronization signal and an electronic device, related to the field of image processing and display technologies. The method includes that the electronic device draws one or more layers in response to a first vertical synchronization signal; and the electronic device renders, in response to a second vertical synchronization signal, the layers drawn by the electronic device.