Vertical Sync Timing Control for Lower Display Response Delay

Solution Overview

Problem

Existing methods to reduce response delay in electronic devices by increasing processor frequency lead to increased power consumption and load, compromising fluency and user experience.

Innovation Solution

A control method utilizing vertical synchronization signals to adjust the timing of image processing stages, specifically delaying the vertical synchronization signal 1 relative to signal 3 to optimize the composition delay without increasing load, thereby improving fluency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the working frequency of the processor is improved to shorten response delay, then the fluency is improved, but the power consumption increases

Engineering Contradiction:

Improveresponse delayVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by adjusting the timing of image processing stages in advance. Specifically, it delays the vertical synchronization signal 1 relative to signal 3 to optimize composition delay, allowing the system to prepare and process images more efficiently before display, thereby reducing overall response delay without requiring increased processor frequency and avoiding additional power consumption

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If the working frequency of the processor is improved to shorten response delay, then the fluency is improved, but the load increases

Engineering Contradiction:

Improveresponse delayVSAvoidload

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by adjusting the timing of image processing stages in advance. Specifically, it delays the vertical synchronization signal 1 relative to signal 3 to optimize composition delay, allowing the system to prepare and process images more efficiently before display, thereby reducing overall response delay without requiring increased processor frequency and avoiding additional load

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies dynamics by dynamically adjusting the timing parameters of vertical synchronization signals. The system optimizes the delay between vertical synchronization signal 1 and signal 3 to improve composition delay, creating a dynamic timing adjustment mechanism that enhances fluency without increasing processor load

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP3971692B1Control method based on vertical synchronizing signal, and electronic device

Publication Date: 2025.08.27 HUAWEI DEVICE CO LTD

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AI summary

Embodiments of this application provide a control method based on a vertical synchronization signal and an electronic device, to shorten a response delay of the electronic device and improve fluency of the electronic device without increasing load of the electronic device. The method may include: drawing, by an electronic device including a display screen, one or more layers in response to a first vertical synchronization signal; refreshing and displaying an image frame in response to a second vertical synchronization signal; adjusting the first vertical synchronization signal, so that the adjusted first vertical synchronization signal is delayed by first delay time relative to the second vertical synchronization signal; and drawing one or more layers in response to the adjusted first vertical synchronization signal.