Vertical TFET Frustoconical Protrusion Leakage Control
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Solution Overview
Problem
As semiconductor components shrink, challenges arise from increased current leakage, signal crossovers, and power usage concerns, which existing tunneling field-effect transistors (TFETs) have not adequately addressed, particularly in maintaining low power supply voltage without substantial off-state leakage currents.
Innovation Solution
A method for fabricating a vertical tunneling field-effect transistor (TFET) device involving a frustoconical protrusion structure on a substrate, with specific doping and isolation dielectric layers, and a gate stack that wraps around the protrusion, enabling efficient power management and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS field-effect transistors are scaled down to increase device density, then the number of interconnected devices per unit area increases, but current leakage and power usage increase significantly
Solution Approach 1:
The patent transitions from planar 2D channel structure to a vertical 3D channel structure by forming a protrusion extending from the substrate surface. This dimensional change enables better gate control over the channel while maintaining scalability, allowing the transistor to achieve lower off-state leakage currents due to improved electrostatic control in the vertical configuration
Solution Approach 2:
The patent modifies the channel structure by creating a protrusion with specific geometric parameters (height, width, aspect ratio) that optimize the gate control efficiency. By changing the physical dimensions and shape parameters of the channel region, the device achieves sub-60 mV/dec subthreshold swing characteristics, enabling lower leakage currents at scaled dimensions
2Use of energy by moving object
If power supply voltage is reduced to lower power consumption, then power usage decreases, but off-state leakage currents increase in existing TFET designs
Solution Approach 1:
The vertical protrusion structure provides enhanced gate control over the channel in the off-state, enabling the transistor to maintain lower leakage currents even at reduced power supply voltages. The three-dimensional gate wrapping around the vertical channel improves electrostatic control compared to planar structures
Solution Approach 2:
By optimizing the protrusion geometry parameters including height-to-width ratio and doping concentration gradients, the device achieves sub-60 mV/dec subthreshold swing that allows operation at lower voltages while maintaining acceptable off-state leakage performance
3Productivity
If feature size is reduced to increase device density, then more devices fit per unit area, but signal crossover and current leakage become more noticeable
Solution Approach 1:
The vertical channel structure separates the current flow path from the planar substrate surface, reducing the likelihood of signal crossover between adjacent devices. The protrusion extends upward, creating physical isolation between neighboring transistors while maintaining compact footprint for high density
Solution Approach 2:
The patent applies localized doping regions with different concentrations in specific areas of the protrusion structure, creating optimized electrical properties in different zones. This local quality variation helps control current confinement and reduce leakage while maintaining signal integrity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables further scaling of power supply voltage with reduced off-state leakage currents, improving the performance and efficiency of TFETs in semiconductor integrated circuits.
Implementation Method 1
tunneling field-effect transistor (TFET) device
Implementation Method 2
sub-60 mV/dec subthreshold swing
Data Source
AI summary
A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.