Vertical TFET with InSb GaSb Heterostructure for High On-State Current
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Solution Overview
Problem
Conventional tunneling field effect transistors (TFETs) have a small on-state current due to limited tunneling area and probability, restricting their application potential.
Innovation Solution
A TFET device is designed with InSb and GaSb material sets, high dielectric constant oxide layers, and specific dopant types, along with a silicon base substrate and SiGe layer, to enhance carrier mobility and on-state current, featuring a complementary structure with trench isolation and high k oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lateral tunneling structure is used, then device structure is simple, but on-state current is undesirably small
Solution Approach 1:
The patent transitions from conventional lateral tunneling to vertical tunneling architecture. The tunnel junction is formed vertically between source and drain regions separated by an ultra-thin barrier layer, enabling carrier tunneling in the vertical direction rather than lateral direction. This dimensional change increases the effective tunneling area and improves on-state current while maintaining manageable device complexity through standard vertical transistor fabrication processes.
Solution Approach 2:
The patent employs composite material structures including heteroepitaxial layers with different bandgaps (e.g., AlGaAs barrier layer between GaAs source and InGaAs channel). This composite structure creates favorable band alignment for enhanced tunneling probability and carrier injection efficiency, directly improving on-state current. The multi-material approach is integrated into existing semiconductor fabrication, avoiding excessive complexity increase.
2Productivity
If tunneling area is increased to improve on-state current, then on-state current increases, but device area increases
Solution Approach 1:
By switching to vertical tunneling architecture, the patent achieves high on-state current density within a compact footprint. The vertical tunnel junction allows the tunneling current to flow through the thickness of the ultra-thin barrier layer rather than requiring large lateral area. This enables high current output from a small device area, effectively decoupling current magnitude from device footprint.
Solution Approach 2:
The patent utilizes parameter optimization including ultra-thin barrier layer thickness (controlling tunneling probability) and high doping concentrations in source and drain regions. By precisely controlling these parameters, high on-state current is achieved without proportionally increasing device area, as the current enhancement comes from improved tunneling efficiency per unit area rather than area expansion.
3Productivity
If conventional TFET structure is used, then manufacturing process is simple, but on-state current is limited by tunneling probability
Solution Approach 1:
The patent implements heteroepitaxial growth with multiple material layers including GaAs, AlGaAs, and InGaAs with specific compositions and thicknesses. This composite material structure is designed to create optimal band alignment and tunneling conditions. The heterostructure enables enhanced tunneling probability and carrier mobility while being fabricated using established semiconductor growth techniques, balancing performance improvement with manufacturing feasibility.
Solution Approach 2:
The patent applies different material compositions and doping concentrations at different locations within the device structure. For example, the barrier layer has specific aluminum content optimized for tunneling, while the channel region has graded composition for carrier transport. This local optimization of material properties throughout the device enables high on-state current while maintaining overall structural integrity and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a substantially high on-state current and mobility, overcoming the limitations of conventional TFETs, enabling wider application of TFET devices.
Implementation Method 1
a first oxide layer disposed between the first channel portion and the first gate member, wherein a dielectric constant of the first oxide layer is greater than or equal to 3.9
Implementation Method 2
a first source portion that includes a first InSb material set and a first first-type dopant set... a first drain portion that includes a second InSb material set and a first second-type dopant set
Data Source
AI summary
A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set.