Vertical TFET Electrode Structure for Higher Line Tunneling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional tunnel field-effect transistors (TFETs) face challenges such as low driving current, high subthreshold swing, complex fabrication processes, large occupied area, small line-tunneling region, and low occurrence probability of line tunneling.
Innovation Solution
The semiconductor device design includes a control-source electrode plate that overlaps the gate structure along the direction of the gate electric field, enhancing the line-tunneling region and occurrence probability. Additionally, one electrode can be designed as a Schottky contact and the other as an Ohmic contact, omitting ion implantation steps and simplifying the process. A charge-enhanced oxide layer is also used to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional PIN TFET structure is used, then the device can be manufactured with standard processes, but the driving current is low and subthreshold swing is high
Solution Approach 1:
The patent transitions from conventional planar TFET structure to a vertical stacked structure where the control electrode extends along the channel length direction. This dimensional change creates a larger overlap area between control and channel regions, enhancing electric field control and line tunneling probability, thereby increasing driving current while maintaining manufacturability
Solution Approach 2:
The control electrode is nested within the vertical stack, extending along the channel length and overlapping the channel region. This nested configuration allows the control electrode to be integrated within the device structure rather than as a separate component, improving both driving current and subthreshold swing while maintaining compact fabrication processes
2Device complexity
If conventional PIN TFET structure is used, then the device structure is simple, but the subthreshold swing is above 60 mV/Dec and driving current is low
Solution Approach 1:
The vertical stacked structure with control electrode extending along channel length creates enhanced electric field control without significantly increasing lateral footprint. This dimensional reconfiguration improves subthreshold swing to below 60 mV/Dec while maintaining relatively simple device geometry
Solution Approach 2:
The patent changes the geometric parameters of the control electrode, specifically extending it along the channel length direction to increase overlap area. This parameter modification enhances the electric field effect and line tunneling probability, improving subthreshold swing and driving current without requiring complex multi-material structures
3Manufacturing precision
If ion implantation technique is used for doping, then precise doping profiles can be achieved, but the fabrication process becomes complex and costly
Solution Approach 1:
The patent extracts the ion implantation step from the fabrication process by using Schottky contacts to induce doping profiles through electric field effects during operation. This removes the complex ion implantation and high-temperature annealing steps while achieving the necessary doping profiles through field-induced carrier injection
Solution Approach 2:
The patent replaces the mechanical ion implantation process with an electrical field-induced doping mechanism. Schottky contacts create strong electric fields that induce carrier injection and form functional doping profiles without physical ion bombardment, simplifying the fabrication process while maintaining manufacturing precision
4Productivity
If line tunneling is used between different doped semiconductors, then driving current can be increased, but the occurrence probability of line tunneling is too small
Solution Approach 1:
The patent extends the control electrode along the channel length direction, creating a larger three-dimensional overlap volume between control and channel regions. This dimensional enhancement increases the probability of line tunneling events by providing more spatial pathways for carrier tunneling, thereby increasing driving current
Solution Approach 2:
The patent employs heterostructure materials with different bandgaps and effective masses to enhance line tunneling probability. The vertical stacked structure combines materials optimized for strong electric field control and high tunneling probability, creating composite regions where line tunneling occurs more frequently to increase driving current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly increases the driving current and lowers the subthreshold swing, simplifies the fabrication process, reduces costs, and improves the overall performance of the semiconductor device.
Implementation Method 1
line tunneling occurs only between semiconductors of different types or different doping, the probability of line tunneling is too small
Implementation Method 2
the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure
Implementation Method 3
one of the control-source electrode plate and the drain electrode can also be designed as the Schottky contact, while the other of the control-source electrode plate and the drain electrode can be designed as the Ohmic contact
Implementation Method 4
The configuration of the Schottky contact forms a dopant inductive region in the semiconductor layer, thereby omitting the step of the ion implantation
Implementation Method 5
the charge-enhanced oxide layer also can be designed to lower the contact area of the Schottky contact, thereby avoiding the issue of the fermi-level pinning at a particular location
Data Source
AI summary
A semiconductor device includes a semiconductor layer, a gate structure, a control-source electrode plate, and a drain electrode. The semiconductor layer has a channel region. The gate structure has a surface to contact the semiconductor layer, in which the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure. The control-source electrode plate is in contact with the semiconductor layer, in which the control-source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure. The drain electrode is in contact with the semiconductor layer.