Vertical TFET with Enlarged Source Contact
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Solution Overview
Problem
As semiconductor integrated circuits shrink, challenges arise from increased current leakage, signal crossovers, and power usage, with existing tunneling field-effect transistors (TFETs) not fully addressing these issues, particularly in maintaining low power supply voltage and minimizing off-state leakage currents.
Innovation Solution
A method for fabricating a vertical TFET device with an enlarged and quasi-self-aligned source contact, involving a frustoconical protrusion structure, a high-k/metal gate stack, and specific doping and etching processes to enhance contact resistance and prevent source-gate shorts, allowing for flexible photolithography and improved process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional MOS field-effect transistors are used, then device scaling is achieved, but off-state leakage currents increase and power usage becomes significant
Solution Approach 1:
The patent changes the fundamental operating mechanism from conventional MOS to tunneling FET, utilizing quantum tunneling effects to achieve sub-60 mV/dec subthreshold swing. This parameter change enables steeper turn-off characteristics and lower off-state leakage currents while maintaining device scaling capability
Solution Approach 2:
The patent replaces the conventional field-effect mechanism with a tunneling mechanism, substituting the traditional charge-based control with quantum mechanical tunneling. This substitution enables better control over carrier transport and reduces off-state leakage while maintaining scalability
2Reliability
If existing tunneling field-effect transistors are implemented, then subthreshold swing is improved, but source-gate short risks and contact resistance issues persist
Solution Approach 1:
The patent transitions from a planar TFET structure to a vertical TFET architecture. This dimensional change separates the source and gate regions in the vertical direction, eliminating source-gate short risks while maintaining the beneficial subthreshold swing characteristics of tunneling FETs
Solution Approach 2:
The patent segments the device into distinct vertical regions including source, channel, and drain sections. This segmentation allows independent optimization of each region and prevents electrical interference between source and gate, eliminating short risks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a vertical TFET device with reduced source-gate short risks and improved contact resistance, enabling further scaling of power supply voltage while minimizing off-state leakage currents.
Implementation Method 1
a high-k/metal gate stack
Implementation Method 2
Tunneling FETs are promising devices that may enable further scaling of power supply voltage without substantially increasing off-state leakage currents due to its sub-60 mV/dec subthreshold swing
Data Source
AI summary
Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.