Vertical TFET Layout for Leveled Source-Drain Formation
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Solution Overview
Problem
Conventional CMOSFETs face challenges in power consumption scaling, and vertical TFETs encounter issues due to the height difference between source and drain, complicating contact formation.
Innovation Solution
A vertical TFET structure is developed with a method that includes forming patterned hard masks, recessing semiconductor mesas, creating isolation features, and forming drain and gate structures to align the source and drain at the same horizontal level, enabling efficient contact formation and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If vertical TFET structure is used to enable power supply voltage scaling, then power consumption is reduced, but contact formation becomes complex due to height difference between source and drain
Solution Approach 1:
The patent applies the equipotentiality principle by raising the source region to the same horizontal level as the drain region through selective epitaxial growth. This creates a planar surface where both source and drain contacts can be formed at the same elevation, eliminating the height difference problem while maintaining the vertical TFET structure's low power consumption benefits
Solution Approach 2:
The patent transitions from a two-dimensional contact formation problem (horizontal plane) to a three-dimensional solution by utilizing vertical epitaxial growth to raise the source region. This dimensional approach allows contacts to be formed on a planar surface while maintaining the vertical channel structure, resolving the complexity issue
2Reliability
If source and drain are at different horizontal levels in vertical TFET, then tunneling effect is achieved, but fabrication process becomes more difficult
Solution Approach 1:
The patent segments the fabrication process into distinct stages: first forming the drain region, then selectively raising the source region through epitaxial growth, and finally forming contacts. This segmentation allows each step to be optimized independently, maintaining tunneling performance while simplifying overall fabrication
Solution Approach 2:
The patent performs preliminary actions by pre-forming the drain region and selectively raising the source region to the same level before contact formation. This preliminary structuring simplifies subsequent contact fabrication processes while ensuring the tunneling junction is properly established
Data Source
AI summary
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.