Vertical TFET SRAM Cell for Packing Density and Variation Control

The patent transitions from a planar U-shaped gate structure to a vertical three-dimensional gate structure. The gate electrode extends vertically through the tunnel barrier layer and semiconductor layer, creating a vertical field effect transistor configuration. This dimensional change allows for improved packing density while reducing device variation through better control of the channel region.

The patent employs composite material structures including a tunnel barrier layer (such as oxide material), semiconductor layer, and gate electrode materials with different properties. The vertical gate structure combines these materials in a stacked configuration, where the gate electrode material interfaces with both the tunnel barrier and semiconductor layers, creating a composite structure that addresses both density and reliability requirements.

By moving to a vertical architecture, the patent decouples the packing density from the planar feature size constraints. The vertical gate structure allows smaller effective channel dimensions without proportionally reducing lithographic feature sizes, thereby maintaining manufacturing precision while achieving higher density through the third dimension.

The patent changes the critical dimension parameter from lateral feature size to vertical layer thickness. The tunnel barrier layer thickness and vertical gate dimensions become the controlling parameters rather than lateral feature sizes, allowing for precise control through atomic layer deposition or molecular beam epitaxy techniques that provide better thickness uniformity.