Vertical TFT Array Substrate for Lower Impedance Displays
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Solution Overview
Problem
Current display devices face higher power consumption due to larger impedance of thin film transistors, which is exacerbated by the multiple thin film transistors required for each pixel.
Innovation Solution
The array substrate is designed with a vertical-structured thin film transistor configuration, where the first and second electrodes are disposed on top and bottom sides of the active layer, respectively, with overlapping portions. This configuration reduces the channel width and area of the thin film transistors, thereby reducing impedance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar thin film transistor structure is used, then the transistor can be easily manufactured, but the transistor area is large causing high impedance and high power consumption
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure by stacking the active layer, first electrode, and second electrode in vertical layers. This dimensional change reduces the transistor footprint area while maintaining electrical functionality, directly addressing the power consumption issue caused by large transistor area in traditional planar designs.
Solution Approach 2:
The patent implements a nested structure where the first electrode is positioned within the vertical space above the active layer, and the second electrode is positioned above the first electrode, creating a compact stacked configuration. This nesting approach maximizes space utilization and reduces the overall transistor area occupation.
2Ease of manufacture
If traditional planar thin film transistor structure is used, then the manufacturing process is simple, but the transistor area is large leading to larger impedance
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure by stacking the active layer, first electrode, and second electrode in vertical layers. This dimensional change reduces the transistor footprint area while maintaining electrical functionality, directly addressing the power consumption issue caused by large transistor area in traditional planar designs.
3Use of energy by moving object
If transistor area is reduced to lower power consumption, then power consumption decreases, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the transistor structure into distinct vertical layers: active layer, first electrode, and second electrode. This segmentation allows each component to be optimized independently while maintaining a compact overall structure, reducing the transistor area and power consumption without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent transitions from a planar two-dimensional transistor structure to a vertical three-dimensional structure by stacking the active layer, first electrode, and second electrode in vertical layers. This dimensional change reduces the transistor footprint area while maintaining electrical functionality, directly addressing the power consumption issue caused by large transistor area in traditional planar designs.
Data Source
AI summary
An array substrate, a manufacturing method thereof, and a display panel are provided. By disposing first electrodes and second electrodes on top and bottom sides of an active layer, respectively, and disposing a part of each gate electrode among sub-active patterns, the array substrate is formed with vertical-structured thin film transistors. Therefore, a channel resistance can be reduced, and a channel width of the thin film transistors can be reduced, thereby reducing an area of the thin film transistors, reducing impedance of the thin film transistors, and reducing power consumption of the display panel.